来自「CPLD的小程序集合」· 代码 · 共 129 行

Timing Analyzer report for mlt
Tue Jun 24 23:12:21 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To   ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 7.727 ns    ; a[0] ; c[7] ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;      ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM240T100C5       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-----------------------------------------------------------+
; tpd                                                       ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To   ;
+-------+-------------------+-----------------+------+------+
; N/A   ; None              ; 7.727 ns        ; a[0] ; c[7] ;
; N/A   ; None              ; 7.726 ns        ; a[0] ; c[4] ;
; N/A   ; None              ; 7.719 ns        ; a[0] ; c[1] ;
; N/A   ; None              ; 7.717 ns        ; a[0] ; c[5] ;
; N/A   ; None              ; 7.593 ns        ; a[1] ; c[6] ;
; N/A   ; None              ; 7.465 ns        ; b[1] ; c[7] ;
; N/A   ; None              ; 7.465 ns        ; b[1] ; c[4] ;
; N/A   ; None              ; 7.458 ns        ; b[1] ; c[1] ;
; N/A   ; None              ; 7.456 ns        ; b[1] ; c[5] ;
; N/A   ; None              ; 7.160 ns        ; a[1] ; c[3] ;
; N/A   ; None              ; 7.152 ns        ; a[1] ; c[2] ;
; N/A   ; None              ; 7.094 ns        ; b[0] ; c[7] ;
; N/A   ; None              ; 7.093 ns        ; b[0] ; c[4] ;
; N/A   ; None              ; 7.086 ns        ; b[0] ; c[1] ;
; N/A   ; None              ; 7.085 ns        ; b[0] ; c[5] ;
; N/A   ; None              ; 6.996 ns        ; b[1] ; c[6] ;
; N/A   ; None              ; 6.898 ns        ; b[0] ; c[6] ;
; N/A   ; None              ; 6.815 ns        ; b[1] ; c[3] ;
; N/A   ; None              ; 6.812 ns        ; b[1] ; c[2] ;
; N/A   ; None              ; 6.809 ns        ; a[0] ; c[6] ;
; N/A   ; None              ; 6.784 ns        ; a[0] ; c[3] ;
; N/A   ; None              ; 6.776 ns        ; a[0] ; c[2] ;
; N/A   ; None              ; 6.592 ns        ; a[1] ; c[7] ;
; N/A   ; None              ; 6.591 ns        ; a[1] ; c[4] ;
; N/A   ; None              ; 6.584 ns        ; a[1] ; c[1] ;
; N/A   ; None              ; 6.582 ns        ; a[1] ; c[5] ;
; N/A   ; None              ; 6.411 ns        ; b[0] ; c[3] ;
; N/A   ; None              ; 6.405 ns        ; b[0] ; c[2] ;
+-------+-------------------+-----------------+------+------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Jun 24 23:12:20 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off mlt -c mlt
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Longest tpd from source pin "a[0]" to destination pin "c[7]" is 7.727 ns
    Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_43; Fanout = 7; PIN Node = 'a[0]'
    Info: 2: + IC(2.747 ns) + CELL(0.914 ns) = 4.793 ns; Loc. = LC_X5_Y4_N0; Fanout = 1; COMB Node = 'Mux0~3'
    Info: 3: + IC(0.612 ns) + CELL(2.322 ns) = 7.727 ns; Loc. = PIN_88; Fanout = 0; PIN Node = 'c[7]'
    Info: Total cell delay = 4.368 ns ( 56.53 % )
    Info: Total interconnect delay = 3.359 ns ( 43.47 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Processing ended: Tue Jun 24 23:12:21 2008
    Info: Elapsed time: 00:00:02