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来自「CPLD的小程序集合」· 代码 · 共 33 行 · 第 1/3 页

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "8.095 ns pin pin " "Info: Estimated most critical path is pin to pin delay of 8.095 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns a\[1\] 1 PIN PIN_56 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_56; Fanout = 1; PIN Node = 'a\[1\]'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { a[1] } "NODE_NAME" } } { "cmp.vhd" "" { Text "D:/EPM240/基础实验/四位比较器/cmp.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.511 ns) + CELL(0.200 ns) 2.843 ns LessThan0~348 2 COMB LAB_X7_Y1 1 " "Info: 2: + IC(1.511 ns) + CELL(0.200 ns) = 2.843 ns; Loc. = LAB_X7_Y1; Fanout = 1; COMB Node = 'LessThan0~348'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "1.711 ns" { a[1] LessThan0~348 } "NODE_NAME" } } { "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" 1695 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.669 ns) + CELL(0.511 ns) 4.023 ns LessThan0~349 3 COMB LAB_X7_Y1 1 " "Info: 3: + IC(0.669 ns) + CELL(0.511 ns) = 4.023 ns; Loc. = LAB_X7_Y1; Fanout = 1; COMB Node = 'LessThan0~349'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "1.180 ns" { LessThan0~348 LessThan0~349 } "NODE_NAME" } } { "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" 1695 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.669 ns) + CELL(0.511 ns) 5.203 ns LessThan0~350 4 COMB LAB_X7_Y1 4 " "Info: 4: + IC(0.669 ns) + CELL(0.511 ns) = 5.203 ns; Loc. = LAB_X7_Y1; Fanout = 4; COMB Node = 'LessThan0~350'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "1.180 ns" { LessThan0~349 LessThan0~350 } "NODE_NAME" } } { "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" 1695 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.570 ns) + CELL(2.322 ns) 8.095 ns c\[2\] 5 PIN PIN_52 0 " "Info: 5: + IC(0.570 ns) + CELL(2.322 ns) = 8.095 ns; Loc. = PIN_52; Fanout = 0; PIN Node = 'c\[2\]'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "2.892 ns" { LessThan0~350 c[2] } "NODE_NAME" } } { "cmp.vhd" "" { Text "D:/EPM240/基础实验/四位比较器/cmp.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.676 ns ( 57.76 % ) " "Info: Total cell delay = 4.676 ns ( 57.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.419 ns ( 42.24 % ) " "Info: Total interconnect delay = 3.419 ns ( 42.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "8.095 ns" { a[1] LessThan0~348 LessThan0~349 LessThan0~350 c[2] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "12 " "Warning: Following 12 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "c\[0\] VCC " "Info: Pin c\[0\] has VCC driving its datain port" {  } { { "cmp.vhd" "" { Text "D:/EPM240/基础实验/四位比较器/cmp.vhd" 10 -1 0 } } { "d:/altera/win/Assignment Editor.qase" "" { Assignment "d:/altera/win/Assignment Editor.qase" 1 { { 0 "c\[0\]" } } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { c[0] } "NODE_NAME" } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { c[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "c\[1\] VCC " "Info: Pin c\[1\] has VCC driving its datain port" {  } { { "cmp.vhd" "" { Text "D:/EPM240/基础实验/四位比较器/cmp.vhd" 10 -1 0 } } { "d:/altera/win/Assignment Editor.qase" "" { Assignment "d:/altera/win/Assignment Editor.qase" 1 { { 0 "c\[1\]" } } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { c[1] } "NODE_NAME" } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { c[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "c\[5\] GND " "Info: Pin c\[5\] has GND driving its datain port" {  } { { "cmp.vhd" "" { Text "D:/EPM240/基础实验/四位比较器/cmp.vhd" 10 -1 0 } } { "d:/altera/win/Assignment Editor.qase" "" { Assignment "d:/altera/win/Assignment Editor.qase" 1 { { 0 "c\[5\]" } } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { c[5] } "NODE_NAME" } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { c[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "c\[6\] GND " "Info: Pin c\[6\] has GND driving its datain port" {  } { { "cmp.vhd" "" { Text "D:/EPM240/基础实验/四位比较器/cmp.vhd" 10 -1 0 } } { "d:/altera/win/Assignment Editor.qase" "" { Assignment "d:/altera/win/Assignment Editor.qase" 1 { { 0 "c\[6\]" } } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { c[6] } "NODE_NAME" } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { c[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[0\] GND " "Info: Pin en\[0\] has GND driving its datain port" {  } { { "cmp.vhd" "" { Text "D:/EPM240/基础实验/四位比较器/cmp.vhd" 11 -1 0 } } { "d:/altera/win/Assignment Editor.qase" "" { Assignment "d:/altera/win/Assignment Editor.qase" 1 { { 0 "en\[0\]" } } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { en[0] } "NODE_NAME" } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { en[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[1\] GND " "Info: Pin en\[1\] has GND driving its datain port" {  } { { "cmp.vhd" "" { Text "D:/EPM240/基础实验/四位比较器/cmp.vhd" 11 -1 0 } } { "d:/altera/win/Assignment Editor.qase" "" { Assignment "d:/altera/win/Assignment Editor.qase" 1 { { 0 "en\[1\]" } } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { en[1] } "NODE_NAME" } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { en[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[2\] GND " "Info: Pin en\[2\] has GND driving its datain port" {  } { { "cmp.vhd" "" { Text "D:/EPM240/基础实验/四位比较器/cmp.vhd" 11 -1 0 } } { "d:/altera/win/Assignment Editor.qase" "" { Assignment "d:/altera/win/Assignment Editor.qase" 1 { { 0 "en\[2\]" } } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { en[2] } "NODE_NAME" } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { en[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[3\] GND " "Info: Pin en\[3\] has GND driving its datain port" {  } { { "cmp.vhd" "" { Text "D:/EPM240/基础实验/四位比较器/cmp.vhd" 11 -1 0 } } { "d:/altera/win/Assignment Editor.qase" "" { Assignment "d:/altera/win/Assignment Editor.qase" 1 { { 0 "en\[3\]" } } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { en[3] } "NODE_NAME" } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { en[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[4\] GND " "Info: Pin en\[4\] has GND driving its datain port" {  } { { "cmp.vhd" "" { Text "D:/EPM240/基础实验/四位比较器/cmp.vhd" 11 -1 0 } } { "d:/altera/win/Assignment Editor.qase" "" { Assignment "d:/altera/win/Assignment Editor.qase" 1 { { 0 "en\[4\]" } } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { en[4] } "NODE_NAME" } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { en[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[5\] GND " "Info: Pin en\[5\] has GND driving its datain port" {  } { { "cmp.vhd" "" { Text "D:/EPM240/基础实验/四位比较器/cmp.vhd" 11 -1 0 } } { "d:/altera/win/Assignment Editor.qase" "" { Assignment "d:/altera/win/Assignment Editor.qase" 1 { { 0 "en\[5\]" } } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { en[5] } "NODE_NAME" } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { en[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[6\] GND " "Info: Pin en\[6\] has GND driving its datain port" {  } { { "cmp.vhd" "" { Text "D:/EPM240/基础实验/四位比较器/cmp.vhd" 11 -1 0 } } { "d:/altera/win/Assignment Editor.qase" "" { Assignment "d:/altera/win/Assignment Editor.qase" 1 { { 0 "en\[6\]" } } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { en[6] } "NODE_NAME" } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { en[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[7\] GND " "Info: Pin en\[7\] has GND driving its datain port" {  } { { "cmp.vhd" "" { Text "D:/EPM240/基础实验/四位比较器/cmp.vhd" 11 -1 0 } } { "d:/altera/win/Assignment Editor.qase" "" { Assignment "d:/altera/win/Assignment Editor.qase" 1 { { 0 "en\[7\]" } } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { en[7] } "NODE_NAME" } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { en[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 24 23:19:05 2008 " "Info: Processing ended: Tue Jun 24 23:19:05 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/EPM240/基础实验/四位比较器/cmp.fit.smsg " "Info: Generated suppressed messages file D:/EPM240/基础实验/四位比较器/cmp.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}