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来自「CPLD的小程序集合」· 代码 · 共 8 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jun 24 23:19:10 2008 " "Info: Processing started: Tue Jun 24 23:19:10 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off cmp -c cmp " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off cmp -c cmp" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "b\[0\] c\[4\] 8.744 ns Longest " "Info: Longest tpd from source pin \"b\[0\]\" to destination pin \"c\[4\]\" is 8.744 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns b\[0\] 1 PIN PIN_55 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_55; Fanout = 1; PIN Node = 'b\[0\]'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { b[0] } "NODE_NAME" } } { "cmp.vhd" "" { Text "D:/EPM240/基础实验/四位比较器/cmp.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.257 ns) + CELL(0.914 ns) 3.303 ns LessThan0~348 2 COMB LC_X7_Y1_N0 1 " "Info: 2: + IC(1.257 ns) + CELL(0.914 ns) = 3.303 ns; Loc. = LC_X7_Y1_N0; Fanout = 1; COMB Node = 'LessThan0~348'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "2.171 ns" { b[0] LessThan0~348 } "NODE_NAME" } } { "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" 1695 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 3.808 ns LessThan0~349 3 COMB LC_X7_Y1_N1 1 " "Info: 3: + IC(0.305 ns) + CELL(0.200 ns) = 3.808 ns; Loc. = LC_X7_Y1_N1; Fanout = 1; COMB Node = 'LessThan0~349'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "0.505 ns" { LessThan0~348 LessThan0~349 } "NODE_NAME" } } { "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" 1695 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.715 ns) + CELL(0.200 ns) 4.723 ns LessThan0~350 4 COMB LC_X7_Y1_N6 4 " "Info: 4: + IC(0.715 ns) + CELL(0.200 ns) = 4.723 ns; Loc. = LC_X7_Y1_N6; Fanout = 4; COMB Node = 'LessThan0~350'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "0.915 ns" { LessThan0~349 LessThan0~350 } "NODE_NAME" } } { "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" 1695 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.699 ns) + CELL(2.322 ns) 8.744 ns c\[4\] 5 PIN PIN_49 0 " "Info: 5: + IC(1.699 ns) + CELL(2.322 ns) = 8.744 ns; Loc. = PIN_49; Fanout = 0; PIN Node = 'c\[4\]'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "4.021 ns" { LessThan0~350 c[4] } "NODE_NAME" } } { "cmp.vhd" "" { Text "D:/EPM240/基础实验/四位比较器/cmp.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.768 ns ( 54.53 % ) " "Info: Total cell delay = 4.768 ns ( 54.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.976 ns ( 45.47 % ) " "Info: Total interconnect delay = 3.976 ns ( 45.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "8.744 ns" { b[0] LessThan0~348 LessThan0~349 LessThan0~350 c[4] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "8.744 ns" { b[0] b[0]~combout LessThan0~348 LessThan0~349 LessThan0~350 c[4] } { 0.000ns 0.000ns 1.257ns 0.305ns 0.715ns 1.699ns } { 0.000ns 1.132ns 0.914ns 0.200ns 0.200ns 2.322ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 24 23:19:10 2008 " "Info: Processing ended: Tue Jun 24 23:19:10 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}