--++

来自「CPLD的小程序集合」· 代码 · 共 135 行

Timing Analyzer report for cmp
Tue Jun 24 23:19:10 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To   ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 8.744 ns    ; b[0] ; c[3] ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;      ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM240T100C5       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-----------------------------------------------------------+
; tpd                                                       ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To   ;
+-------+-------------------+-----------------+------+------+
; N/A   ; None              ; 8.744 ns        ; b[0] ; c[4] ;
; N/A   ; None              ; 8.744 ns        ; b[0] ; c[3] ;
; N/A   ; None              ; 8.611 ns        ; b[1] ; c[4] ;
; N/A   ; None              ; 8.611 ns        ; b[1] ; c[3] ;
; N/A   ; None              ; 8.561 ns        ; a[2] ; c[4] ;
; N/A   ; None              ; 8.561 ns        ; a[2] ; c[3] ;
; N/A   ; None              ; 8.527 ns        ; b[2] ; c[4] ;
; N/A   ; None              ; 8.527 ns        ; b[2] ; c[3] ;
; N/A   ; None              ; 8.349 ns        ; a[0] ; c[4] ;
; N/A   ; None              ; 8.349 ns        ; a[0] ; c[3] ;
; N/A   ; None              ; 8.308 ns        ; b[0] ; c[2] ;
; N/A   ; None              ; 8.175 ns        ; b[1] ; c[2] ;
; N/A   ; None              ; 8.125 ns        ; a[2] ; c[2] ;
; N/A   ; None              ; 8.091 ns        ; b[2] ; c[2] ;
; N/A   ; None              ; 8.070 ns        ; a[1] ; c[4] ;
; N/A   ; None              ; 8.070 ns        ; a[1] ; c[3] ;
; N/A   ; None              ; 7.966 ns        ; b[3] ; c[4] ;
; N/A   ; None              ; 7.966 ns        ; b[3] ; c[3] ;
; N/A   ; None              ; 7.913 ns        ; a[0] ; c[2] ;
; N/A   ; None              ; 7.807 ns        ; a[3] ; c[4] ;
; N/A   ; None              ; 7.807 ns        ; a[3] ; c[3] ;
; N/A   ; None              ; 7.685 ns        ; b[0] ; c[7] ;
; N/A   ; None              ; 7.634 ns        ; a[1] ; c[2] ;
; N/A   ; None              ; 7.552 ns        ; b[1] ; c[7] ;
; N/A   ; None              ; 7.530 ns        ; b[3] ; c[2] ;
; N/A   ; None              ; 7.502 ns        ; a[2] ; c[7] ;
; N/A   ; None              ; 7.468 ns        ; b[2] ; c[7] ;
; N/A   ; None              ; 7.371 ns        ; a[3] ; c[2] ;
; N/A   ; None              ; 7.290 ns        ; a[0] ; c[7] ;
; N/A   ; None              ; 7.011 ns        ; a[1] ; c[7] ;
; N/A   ; None              ; 6.907 ns        ; b[3] ; c[7] ;
; N/A   ; None              ; 6.748 ns        ; a[3] ; c[7] ;
+-------+-------------------+-----------------+------+------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Jun 24 23:19:10 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off cmp -c cmp
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Longest tpd from source pin "b[0]" to destination pin "c[4]" is 8.744 ns
    Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_55; Fanout = 1; PIN Node = 'b[0]'
    Info: 2: + IC(1.257 ns) + CELL(0.914 ns) = 3.303 ns; Loc. = LC_X7_Y1_N0; Fanout = 1; COMB Node = 'LessThan0~348'
    Info: 3: + IC(0.305 ns) + CELL(0.200 ns) = 3.808 ns; Loc. = LC_X7_Y1_N1; Fanout = 1; COMB Node = 'LessThan0~349'
    Info: 4: + IC(0.715 ns) + CELL(0.200 ns) = 4.723 ns; Loc. = LC_X7_Y1_N6; Fanout = 4; COMB Node = 'LessThan0~350'
    Info: 5: + IC(1.699 ns) + CELL(2.322 ns) = 8.744 ns; Loc. = PIN_49; Fanout = 0; PIN Node = 'c[4]'
    Info: Total cell delay = 4.768 ns ( 54.53 % )
    Info: Total interconnect delay = 3.976 ns ( 45.47 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Processing ended: Tue Jun 24 23:19:10 2008
    Info: Elapsed time: 00:00:01