8++

CPLD的小程序集合

{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "10.152 ns pin pin " "Info: Estimated most critical path is pin to pin delay of 10.152 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns a\[0\] 1 PIN PIN_12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_12; Fanout = 1; PIN Node = 'a\[0\]'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { a[0] } "NODE_NAME" } } { "encode.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/基础实验/8位优先编码器/encode.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.776 ns) + CELL(0.740 ns) 3.648 ns c_tmp~366 2 COMB LAB_X2_Y1 1 " "Info: 2: + IC(1.776 ns) + CELL(0.740 ns) = 3.648 ns; Loc. = LAB_X2_Y1; Fanout = 1; COMB Node = 'c_tmp~366'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "2.516 ns" { a[0] c_tmp~366 } "NODE_NAME" } } { "encode.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/基础实验/8位优先编码器/encode.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.980 ns) + CELL(0.200 ns) 4.828 ns c_tmp~367 3 COMB LAB_X2_Y1 4 " "Info: 3: + IC(0.980 ns) + CELL(0.200 ns) = 4.828 ns; Loc. = LAB_X2_Y1; Fanout = 4; COMB Node = 'c_tmp~367'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "1.180 ns" { c_tmp~366 c_tmp~367 } "NODE_NAME" } } { "encode.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/基础实验/8位优先编码器/encode.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.980 ns) + CELL(0.200 ns) 6.008 ns Mux3~136 4 COMB LAB_X2_Y1 1 " "Info: 4: + IC(0.980 ns) + CELL(0.200 ns) = 6.008 ns; Loc. = LAB_X2_Y1; Fanout = 1; COMB Node = 'Mux3~136'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "1.180 ns" { c_tmp~367 Mux3~136 } "NODE_NAME" } } { "encode.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/基础实验/8位优先编码器/encode.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.822 ns) + CELL(2.322 ns) 10.152 ns c\[4\] 5 PIN PIN_98 0 " "Info: 5: + IC(1.822 ns) + CELL(2.322 ns) = 10.152 ns; Loc. = PIN_98; Fanout = 0; PIN Node = 'c\[4\]'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "4.144 ns" { Mux3~136 c[4] } "NODE_NAME" } } { "encode.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/基础实验/8位优先编码器/encode.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.594 ns ( 45.25 % ) " "Info: Total cell delay = 4.594 ns ( 45.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.558 ns ( 54.75 % ) " "Info: Total interconnect delay = 5.558 ns ( 54.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "10.152 ns" { a[0] c_tmp~366 c_tmp~367 Mux3~136 c[4] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "9 " "Warning: Following 9 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "c\[0\] VCC " "Info: Pin c\[0\] has VCC driving its datain port" {  } { { "encode.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/基础实验/8位优先编码器/encode.vhd" 8 -1 0 } } { "d:/altera/win/Assignment Editor.qase" "" { Assignment "d:/altera/win/Assignment Editor.qase" 1 { { 0 "c\[0\]" } } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { c[0] } "NODE_NAME" } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { c[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[0\] GND " "Info: Pin en\[0\] has GND driving its datain port" {  } { { "encode.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/基础实验/8位优先编码器/encode.vhd" 9 -1 0 } } { "d:/altera/win/Assignment Editor.qase" "" { Assignment "d:/altera/win/Assignment Editor.qase" 1 { { 0 "en\[0\]" } } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { en[0] } "NODE_NAME" } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { en[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[1\] GND " "Info: Pin en\[1\] has GND driving its datain port" {  } { { "encode.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/基础实验/8位优先编码器/encode.vhd" 9 -1 0 } } { "d:/altera/win/Assignment Editor.qase" "" { Assignment "d:/altera/win/Assignment Editor.qase" 1 { { 0 "en\[1\]" } } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { en[1] } "NODE_NAME" } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { en[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[2\] GND " "Info: Pin en\[2\] has GND driving its datain port" {  } { { "encode.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/基础实验/8位优先编码器/encode.vhd" 9 -1 0 } } { "d:/altera/win/Assignment Editor.qase" "" { Assignment "d:/altera/win/Assignment Editor.qase" 1 { { 0 "en\[2\]" } } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { en[2] } "NODE_NAME" } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { en[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[3\] GND " "Info: Pin en\[3\] has GND driving its datain port" {  } { { "encode.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/基础实验/8位优先编码器/encode.vhd" 9 -1 0 } } { "d:/altera/win/Assignment Editor.qase" "" { Assignment "d:/altera/win/Assignment Editor.qase" 1 { { 0 "en\[3\]" } } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { en[3] } "NODE_NAME" } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { en[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[4\] GND " "Info: Pin en\[4\] has GND driving its datain port" {  } { { "encode.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/基础实验/8位优先编码器/encode.vhd" 9 -1 0 } } { "d:/altera/win/Assignment Editor.qase" "" { Assignment "d:/altera/win/Assignment Editor.qase" 1 { { 0 "en\[4\]" } } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { en[4] } "NODE_NAME" } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { en[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[5\] GND " "Info: Pin en\[5\] has GND driving its datain port" {  } { { "encode.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/基础实验/8位优先编码器/encode.vhd" 9 -1 0 } } { "d:/altera/win/Assignment Editor.qase" "" { Assignment "d:/altera/win/Assignment Editor.qase" 1 { { 0 "en\[5\]" } } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { en[5] } "NODE_NAME" } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { en[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[6\] GND " "Info: Pin en\[6\] has GND driving its datain port" {  } { { "encode.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/基础实验/8位优先编码器/encode.vhd" 9 -1 0 } } { "d:/altera/win/Assignment Editor.qase" "" { Assignment "d:/altera/win/Assignment Editor.qase" 1 { { 0 "en\[6\]" } } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { en[6] } "NODE_NAME" } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { en[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en\[7\] GND " "Info: Pin en\[7\] has GND driving its datain port" {  } { { "encode.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/基础实验/8位优先编码器/encode.vhd" 9 -1 0 } } { "d:/altera/win/Assignment Editor.qase" "" { Assignment "d:/altera/win/Assignment Editor.qase" 1 { { 0 "en\[7\]" } } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { en[7] } "NODE_NAME" } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { en[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 24 23:10:59 2008 " "Info: Processing ended: Tue Jun 24 23:10:59 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/61EDA_L124/VHDL_Development_Board_Sources/基础实验/8位优先编码器/encode.fit.smsg " "Info: Generated suppressed messages file D:/61EDA_L124/VHDL_Development_Board_Sources/基础实验/8位优先编码器/encode.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}