8++

来自「CPLD的小程序集合」· 代码 · 共 8 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jun 24 23:11:05 2008 " "Info: Processing started: Tue Jun 24 23:11:05 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off encode -c encode " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off encode -c encode" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "a\[3\] c\[3\] 10.310 ns Longest " "Info: Longest tpd from source pin \"a\[3\]\" to destination pin \"c\[3\]\" is 10.310 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns a\[3\] 1 PIN PIN_33 5 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_33; Fanout = 5; PIN Node = 'a\[3\]'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { a[3] } "NODE_NAME" } } { "encode.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/基础实验/8位优先编码器/encode.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.252 ns) + CELL(0.200 ns) 3.584 ns c_tmp~364 2 COMB LC_X2_Y1_N8 1 " "Info: 2: + IC(2.252 ns) + CELL(0.200 ns) = 3.584 ns; Loc. = LC_X2_Y1_N8; Fanout = 1; COMB Node = 'c_tmp~364'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "2.452 ns" { a[3] c_tmp~364 } "NODE_NAME" } } { "encode.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/基础实验/8位优先编码器/encode.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.743 ns) + CELL(0.200 ns) 4.527 ns c_tmp~365 3 COMB LC_X2_Y1_N0 4 " "Info: 3: + IC(0.743 ns) + CELL(0.200 ns) = 4.527 ns; Loc. = LC_X2_Y1_N0; Fanout = 4; COMB Node = 'c_tmp~365'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "0.943 ns" { c_tmp~364 c_tmp~365 } "NODE_NAME" } } { "encode.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/基础实验/8位优先编码器/encode.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.824 ns) + CELL(0.511 ns) 5.862 ns Mux4~41 4 COMB LC_X2_Y1_N7 1 " "Info: 4: + IC(0.824 ns) + CELL(0.511 ns) = 5.862 ns; Loc. = LC_X2_Y1_N7; Fanout = 1; COMB Node = 'Mux4~41'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "1.335 ns" { c_tmp~365 Mux4~41 } "NODE_NAME" } } { "encode.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/基础实验/8位优先编码器/encode.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.126 ns) + CELL(2.322 ns) 10.310 ns c\[3\] 5 PIN PIN_2 0 " "Info: 5: + IC(2.126 ns) + CELL(2.322 ns) = 10.310 ns; Loc. = PIN_2; Fanout = 0; PIN Node = 'c\[3\]'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "4.448 ns" { Mux4~41 c[3] } "NODE_NAME" } } { "encode.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/基础实验/8位优先编码器/encode.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.365 ns ( 42.34 % ) " "Info: Total cell delay = 4.365 ns ( 42.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.945 ns ( 57.66 % ) " "Info: Total interconnect delay = 5.945 ns ( 57.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "10.310 ns" { a[3] c_tmp~364 c_tmp~365 Mux4~41 c[3] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "10.310 ns" { a[3] a[3]~combout c_tmp~364 c_tmp~365 Mux4~41 c[3] } { 0.000ns 0.000ns 2.252ns 0.743ns 0.824ns 2.126ns } { 0.000ns 1.132ns 0.200ns 0.200ns 0.511ns 2.322ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 24 23:11:05 2008 " "Info: Processing ended: Tue Jun 24 23:11:05 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}