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Timing Analyzer report for encode
Tue Jun 24 23:11:05 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 10.310 ns ; a[3] ; c[3] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EPM240T100C5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+-----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+------+
; N/A ; None ; 10.310 ns ; a[3] ; c[3] ;
; N/A ; None ; 10.274 ns ; a[3] ; c[4] ;
; N/A ; None ; 10.226 ns ; a[3] ; c[7] ;
; N/A ; None ; 10.178 ns ; a[4] ; c[3] ;
; N/A ; None ; 10.151 ns ; a[4] ; c[4] ;
; N/A ; None ; 10.112 ns ; a[4] ; c[7] ;
; N/A ; None ; 10.035 ns ; a[6] ; c[3] ;
; N/A ; None ; 10.034 ns ; a[2] ; c[3] ;
; N/A ; None ; 9.999 ns ; a[6] ; c[4] ;
; N/A ; None ; 9.998 ns ; a[2] ; c[4] ;
; N/A ; None ; 9.969 ns ; a[5] ; c[3] ;
; N/A ; None ; 9.951 ns ; a[6] ; c[7] ;
; N/A ; None ; 9.950 ns ; a[2] ; c[7] ;
; N/A ; None ; 9.942 ns ; a[5] ; c[4] ;
; N/A ; None ; 9.935 ns ; a[3] ; c[2] ;
; N/A ; None ; 9.903 ns ; a[5] ; c[7] ;
; N/A ; None ; 9.808 ns ; a[0] ; c[3] ;
; N/A ; None ; 9.804 ns ; a[4] ; c[2] ;
; N/A ; None ; 9.801 ns ; a[1] ; c[3] ;
; N/A ; None ; 9.765 ns ; a[1] ; c[4] ;
; N/A ; None ; 9.732 ns ; a[0] ; c[7] ;
; N/A ; None ; 9.717 ns ; a[1] ; c[7] ;
; N/A ; None ; 9.660 ns ; a[6] ; c[2] ;
; N/A ; None ; 9.659 ns ; a[2] ; c[2] ;
; N/A ; None ; 9.595 ns ; a[5] ; c[2] ;
; N/A ; None ; 9.434 ns ; a[0] ; c[2] ;
; N/A ; None ; 9.426 ns ; a[1] ; c[2] ;
; N/A ; None ; 9.321 ns ; a[0] ; c[4] ;
; N/A ; None ; 9.003 ns ; a[3] ; c[5] ;
; N/A ; None ; 8.829 ns ; a[2] ; c[5] ;
; N/A ; None ; 8.779 ns ; a[1] ; c[1] ;
; N/A ; None ; 8.658 ns ; a[3] ; c[1] ;
; N/A ; None ; 8.620 ns ; a[2] ; c[1] ;
; N/A ; None ; 8.619 ns ; a[7] ; c[5] ;
; N/A ; None ; 8.597 ns ; a[7] ; c[3] ;
; N/A ; None ; 8.561 ns ; a[7] ; c[4] ;
; N/A ; None ; 8.516 ns ; a[7] ; c[7] ;
; N/A ; None ; 8.502 ns ; a[1] ; c[5] ;
; N/A ; None ; 8.339 ns ; a[7] ; c[1] ;
; N/A ; None ; 8.246 ns ; a[6] ; c[1] ;
; N/A ; None ; 8.222 ns ; a[7] ; c[2] ;
; N/A ; None ; 8.131 ns ; a[5] ; c[1] ;
; N/A ; None ; 8.067 ns ; a[4] ; c[1] ;
; N/A ; None ; 8.032 ns ; a[4] ; c[5] ;
; N/A ; None ; 8.023 ns ; a[6] ; c[5] ;
; N/A ; None ; 7.908 ns ; a[5] ; c[5] ;
; N/A ; None ; 6.916 ns ; a[4] ; c[6] ;
; N/A ; None ; 6.906 ns ; a[6] ; c[6] ;
; N/A ; None ; 6.790 ns ; a[5] ; c[6] ;
; N/A ; None ; 6.307 ns ; a[7] ; c[6] ;
+-------+-------------------+-----------------+------+------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Tue Jun 24 23:11:05 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off encode -c encode
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Longest tpd from source pin "a[3]" to destination pin "c[3]" is 10.310 ns
Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_33; Fanout = 5; PIN Node = 'a[3]'
Info: 2: + IC(2.252 ns) + CELL(0.200 ns) = 3.584 ns; Loc. = LC_X2_Y1_N8; Fanout = 1; COMB Node = 'c_tmp~364'
Info: 3: + IC(0.743 ns) + CELL(0.200 ns) = 4.527 ns; Loc. = LC_X2_Y1_N0; Fanout = 4; COMB Node = 'c_tmp~365'
Info: 4: + IC(0.824 ns) + CELL(0.511 ns) = 5.862 ns; Loc. = LC_X2_Y1_N7; Fanout = 1; COMB Node = 'Mux4~41'
Info: 5: + IC(2.126 ns) + CELL(2.322 ns) = 10.310 ns; Loc. = PIN_2; Fanout = 0; PIN Node = 'c[3]'
Info: Total cell delay = 4.365 ns ( 42.34 % )
Info: Total interconnect delay = 5.945 ns ( 57.66 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Tue Jun 24 23:11:05 2008
Info: Elapsed time: 00:00:01
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