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来自「CPLD的小程序集合」· 代码 · 共 366 行 · 第 1/5 页

+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 14.845 ns  ; led1[6]~reg0 ; led1[6] ; clk        ;
; N/A   ; None         ; 14.715 ns  ; led1[5]~reg0 ; led1[5] ; clk        ;
; N/A   ; None         ; 14.670 ns  ; led1[0]~reg0 ; led1[0] ; clk        ;
; N/A   ; None         ; 14.600 ns  ; led1[1]~reg0 ; led1[1] ; clk        ;
; N/A   ; None         ; 14.597 ns  ; led1[3]~reg0 ; led1[3] ; clk        ;
; N/A   ; None         ; 14.587 ns  ; led1[2]~reg0 ; led1[2] ; clk        ;
; N/A   ; None         ; 14.584 ns  ; led1[4]~reg0 ; led1[4] ; clk        ;
; N/A   ; None         ; 13.413 ns  ; led1[7]~reg0 ; led1[7] ; clk        ;
+-------+--------------+------------+--------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Wed Feb 11 23:17:19 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off liushuideng -c liushuideng
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "clk1" as buffer
    Info: Detected ripple clock "CLK2" as buffer
Info: Clock "clk" has Internal fmax of 114.86 MHz between source register "\P1:count[8]" and destination register "\P1:count[19]" (period= 8.706 ns)
    Info: + Longest register to register delay is 7.997 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y3_N8; Fanout = 5; REG Node = '\P1:count[8]'
        Info: 2: + IC(1.347 ns) + CELL(0.740 ns) = 2.087 ns; Loc. = LC_X3_Y3_N7; Fanout = 1; COMB Node = 'count~341'
        Info: 3: + IC(0.788 ns) + CELL(0.511 ns) = 3.386 ns; Loc. = LC_X3_Y3_N4; Fanout = 1; COMB Node = 'count~342'
        Info: 4: + IC(0.534 ns) + CELL(0.200 ns) = 4.120 ns; Loc. = LC_X3_Y3_N5; Fanout = 2; COMB Node = 'count~343'
        Info: 5: + IC(0.305 ns) + CELL(0.200 ns) = 4.625 ns; Loc. = LC_X3_Y3_N6; Fanout = 20; COMB Node = 'count~344'
        Info: 6: + IC(1.612 ns) + CELL(1.760 ns) = 7.997 ns; Loc. = LC_X5_Y3_N9; Fanout = 4; REG Node = '\P1:count[19]'
        Info: Total cell delay = 3.411 ns ( 42.65 % )
        Info: Total interconnect delay = 4.586 ns ( 57.35 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 21; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y3_N9; Fanout = 4; REG Node = '\P1:count[19]'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
        Info: - Longest clock path from clock "clk" to source register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 21; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y3_N8; Fanout = 5; REG Node = '\P1:count[8]'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "clk" to destination pin "led1[6]" through register "led1[6]~reg0" is 14.845 ns
    Info: + Longest clock path from clock "clk" to source register is 9.948 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 21; CLK Node = 'clk'
        Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X3_Y3_N9; Fanout = 2; REG Node = 'clk1'
        Info: 3: + IC(1.264 ns) + CELL(1.294 ns) = 6.282 ns; Loc. = LC_X2_Y3_N2; Fanout = 14; REG Node = 'CLK2'
        Info: 4: + IC(2.748 ns) + CELL(0.918 ns) = 9.948 ns; Loc. = LC_X7_Y3_N8; Fanout = 1; REG Node = 'led1[6]~reg0'
        Info: Total cell delay = 4.669 ns ( 46.93 % )
        Info: Total interconnect delay = 5.279 ns ( 53.07 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 4.521 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y3_N8; Fanout = 1; REG Node = 'led1[6]~reg0'
        Info: 2: + IC(2.199 ns) + CELL(2.322 ns) = 4.521 ns; Loc. = PIN_55; Fanout = 0; PIN Node = 'led1[6]'
        Info: Total cell delay = 2.322 ns ( 51.36 % )
        Info: Total interconnect delay = 2.199 ns ( 48.64 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Wed Feb 11 23:17:19 2009
    Info: Elapsed time: 00:00:01