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来自「CPLD的小程序集合」· 代码 · 共 11 行 · 第 1/2 页

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register cnt\[14\] register en_tmp\[1\] 123.73 MHz 8.082 ns Internal " "Info: Clock \"clk\" has Internal fmax of 123.73 MHz between source register \"cnt\[14\]\" and destination register \"en_tmp\[1\]\" (period= 8.082 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.373 ns + Longest register register " "Info: + Longest register to register delay is 7.373 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[14\] 1 REG LC_X6_Y4_N6 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y4_N6; Fanout = 3; REG Node = 'cnt\[14\]'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { cnt[14] } "NODE_NAME" } } { "bcd.vhd" "" { Text "D:/EPM240/基础实验/二进制转BCD码/bcd.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.881 ns) + CELL(0.914 ns) 1.795 ns Equal0~195 2 COMB LC_X6_Y4_N0 1 " "Info: 2: + IC(0.881 ns) + CELL(0.914 ns) = 1.795 ns; Loc. = LC_X6_Y4_N0; Fanout = 1; COMB Node = 'Equal0~195'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "1.795 ns" { cnt[14] Equal0~195 } "NODE_NAME" } } { "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.022 ns) + CELL(0.511 ns) 4.328 ns Equal0~197 3 COMB LC_X5_Y2_N3 4 " "Info: 3: + IC(2.022 ns) + CELL(0.511 ns) = 4.328 ns; Loc. = LC_X5_Y2_N3; Fanout = 4; COMB Node = 'Equal0~197'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "2.533 ns" { Equal0~195 Equal0~197 } "NODE_NAME" } } { "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.802 ns) + CELL(1.243 ns) 7.373 ns en_tmp\[1\] 4 REG LC_X5_Y3_N8 4 " "Info: 4: + IC(1.802 ns) + CELL(1.243 ns) = 7.373 ns; Loc. = LC_X5_Y3_N8; Fanout = 4; REG Node = 'en_tmp\[1\]'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "3.045 ns" { Equal0~197 en_tmp[1] } "NODE_NAME" } } { "bcd.vhd" "" { Text "D:/EPM240/基础实验/二进制转BCD码/bcd.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.668 ns ( 36.19 % ) " "Info: Total cell delay = 2.668 ns ( 36.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.705 ns ( 63.81 % ) " "Info: Total interconnect delay = 4.705 ns ( 63.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "7.373 ns" { cnt[14] Equal0~195 Equal0~197 en_tmp[1] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "7.373 ns" { cnt[14] Equal0~195 Equal0~197 en_tmp[1] } { 0.000ns 0.881ns 2.022ns 1.802ns } { 0.000ns 0.914ns 0.511ns 1.243ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 22 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 22; CLK Node = 'clk'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "bcd.vhd" "" { Text "D:/EPM240/基础实验/二进制转BCD码/bcd.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns en_tmp\[1\] 2 REG LC_X5_Y3_N8 4 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y3_N8; Fanout = 4; REG Node = 'en_tmp\[1\]'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk en_tmp[1] } "NODE_NAME" } } { "bcd.vhd" "" { Text "D:/EPM240/基础实验/二进制转BCD码/bcd.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk en_tmp[1] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout en_tmp[1] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 22 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 22; CLK Node = 'clk'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "bcd.vhd" "" { Text "D:/EPM240/基础实验/二进制转BCD码/bcd.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns cnt\[14\] 2 REG LC_X6_Y4_N6 3 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X6_Y4_N6; Fanout = 3; REG Node = 'cnt\[14\]'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk cnt[14] } "NODE_NAME" } } { "bcd.vhd" "" { Text "D:/EPM240/基础实验/二进制转BCD码/bcd.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt[14] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout cnt[14] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk en_tmp[1] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout en_tmp[1] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt[14] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout cnt[14] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "bcd.vhd" "" { Text "D:/EPM240/基础实验/二进制转BCD码/bcd.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "bcd.vhd" "" { Text "D:/EPM240/基础实验/二进制转BCD码/bcd.vhd" 43 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "7.373 ns" { cnt[14] Equal0~195 Equal0~197 en_tmp[1] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "7.373 ns" { cnt[14] Equal0~195 Equal0~197 en_tmp[1] } { 0.000ns 0.881ns 2.022ns 1.802ns } { 0.000ns 0.914ns 0.511ns 1.243ns } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk en_tmp[1] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout en_tmp[1] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk cnt[14] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout cnt[14] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk c\[2\] en_tmp\[0\] 12.851 ns register " "Info: tco from clock \"clk\" to destination pin \"c\[2\]\" through register \"en_tmp\[0\]\" is 12.851 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_14 22 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 22; CLK Node = 'clk'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "bcd.vhd" "" { Text "D:/EPM240/基础实验/二进制转BCD码/bcd.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns en_tmp\[0\] 2 REG LC_X5_Y3_N0 4 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y3_N0; Fanout = 4; REG Node = 'en_tmp\[0\]'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk en_tmp[0] } "NODE_NAME" } } { "bcd.vhd" "" { Text "D:/EPM240/基础实验/二进制转BCD码/bcd.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk en_tmp[0] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout en_tmp[0] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "bcd.vhd" "" { Text "D:/EPM240/基础实验/二进制转BCD码/bcd.vhd" 43 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.127 ns + Longest register pin " "Info: + Longest register to pin delay is 9.127 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns en_tmp\[0\] 1 REG LC_X5_Y3_N0 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y3_N0; Fanout = 4; REG Node = 'en_tmp\[0\]'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { en_tmp[0] } "NODE_NAME" } } { "bcd.vhd" "" { Text "D:/EPM240/基础实验/二进制转BCD码/bcd.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.995 ns) + CELL(0.511 ns) 1.506 ns Mux0~33 2 COMB LC_X5_Y3_N1 4 " "Info: 2: + IC(0.995 ns) + CELL(0.511 ns) = 1.506 ns; Loc. = LC_X5_Y3_N1; Fanout = 4; COMB Node = 'Mux0~33'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "1.506 ns" { en_tmp[0] Mux0~33 } "NODE_NAME" } } { "bcd.vhd" "" { Text "D:/EPM240/基础实验/二进制转BCD码/bcd.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.200 ns) 2.480 ns Mux0~34 3 COMB LC_X5_Y3_N4 7 " "Info: 3: + IC(0.774 ns) + CELL(0.200 ns) = 2.480 ns; Loc. = LC_X5_Y3_N4; Fanout = 7; COMB Node = 'Mux0~34'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "0.974 ns" { Mux0~33 Mux0~34 } "NODE_NAME" } } { "bcd.vhd" "" { Text "D:/EPM240/基础实验/二进制转BCD码/bcd.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.716 ns) + CELL(0.914 ns) 5.110 ns Mux13~15 4 COMB LC_X6_Y3_N9 1 " "Info: 4: + IC(1.716 ns) + CELL(0.914 ns) = 5.110 ns; Loc. = LC_X6_Y3_N9; Fanout = 1; COMB Node = 'Mux13~15'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "2.630 ns" { Mux0~34 Mux13~15 } "NODE_NAME" } } { "bcd.vhd" "" { Text "D:/EPM240/基础实验/二进制转BCD码/bcd.vhd" 93 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.695 ns) + CELL(2.322 ns) 9.127 ns c\[2\] 5 PIN PIN_69 0 " "Info: 5: + IC(1.695 ns) + CELL(2.322 ns) = 9.127 ns; Loc. = PIN_69; Fanout = 0; PIN Node = 'c\[2\]'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "4.017 ns" { Mux13~15 c[2] } "NODE_NAME" } } { "bcd.vhd" "" { Text "D:/EPM240/基础实验/二进制转BCD码/bcd.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.947 ns ( 43.25 % ) " "Info: Total cell delay = 3.947 ns ( 43.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.180 ns ( 56.75 % ) " "Info: Total interconnect delay = 5.180 ns ( 56.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "9.127 ns" { en_tmp[0] Mux0~33 Mux0~34 Mux13~15 c[2] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "9.127 ns" { en_tmp[0] Mux0~33 Mux0~34 Mux13~15 c[2] } { 0.000ns 0.995ns 0.774ns 1.716ns 1.695ns } { 0.000ns 0.511ns 0.200ns 0.914ns 2.322ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk en_tmp[0] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout en_tmp[0] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "9.127 ns" { en_tmp[0] Mux0~33 Mux0~34 Mux13~15 c[2] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "9.127 ns" { en_tmp[0] Mux0~33 Mux0~34 Mux13~15 c[2] } { 0.000ns 0.995ns 0.774ns 1.716ns 1.695ns } { 0.000ns 0.511ns 0.200ns 0.914ns 2.322ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "a\[1\] c\[2\] 10.750 ns Longest " "Info: Longest tpd from source pin \"a\[1\]\" to destination pin \"c\[2\]\" is 10.750 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns a\[1\] 1 PIN PIN_81 4 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_81; Fanout = 4; PIN Node = 'a\[1\]'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { a[1] } "NODE_NAME" } } { "bcd.vhd" "" { Text "D:/EPM240/基础实验/二进制转BCD码/bcd.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.231 ns) + CELL(0.740 ns) 4.103 ns Mux0~34 2 COMB LC_X5_Y3_N4 7 " "Info: 2: + IC(2.231 ns) + CELL(0.740 ns) = 4.103 ns; Loc. = LC_X5_Y3_N4; Fanout = 7; COMB Node = 'Mux0~34'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "2.971 ns" { a[1] Mux0~34 } "NODE_NAME" } } { "bcd.vhd" "" { Text "D:/EPM240/基础实验/二进制转BCD码/bcd.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.716 ns) + CELL(0.914 ns) 6.733 ns Mux13~15 3 COMB LC_X6_Y3_N9 1 " "Info: 3: + IC(1.716 ns) + CELL(0.914 ns) = 6.733 ns; Loc. = LC_X6_Y3_N9; Fanout = 1; COMB Node = 'Mux13~15'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "2.630 ns" { Mux0~34 Mux13~15 } "NODE_NAME" } } { "bcd.vhd" "" { Text "D:/EPM240/基础实验/二进制转BCD码/bcd.vhd" 93 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.695 ns) + CELL(2.322 ns) 10.750 ns c\[2\] 4 PIN PIN_69 0 " "Info: 4: + IC(1.695 ns) + CELL(2.322 ns) = 10.750 ns; Loc. = PIN_69; Fanout = 0; PIN Node = 'c\[2\]'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "4.017 ns" { Mux13~15 c[2] } "NODE_NAME" } } { "bcd.vhd" "" { Text "D:/EPM240/基础实验/二进制转BCD码/bcd.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.108 ns ( 47.52 % ) " "Info: Total cell delay = 5.108 ns ( 47.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.642 ns ( 52.48 % ) " "Info: Total interconnect delay = 5.642 ns ( 52.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "10.750 ns" { a[1] Mux0~34 Mux13~15 c[2] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "10.750 ns" { a[1] a[1]~combout Mux0~34 Mux13~15 c[2] } { 0.000ns 0.000ns 2.231ns 1.716ns 1.695ns } { 0.000ns 1.132ns 0.740ns 0.914ns 2.322ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 24 23:15:29 2008 " "Info: Processing ended: Tue Jun 24 23:15:29 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}