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来自「CPLD的小程序集合」· 代码 · 共 730 行 · 第 1/4 页

+-------------------------------------------------------------------------+
; Fitter Device Options                                                   ;
+----------------------------------------------+--------------------------+
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Passive Serial           ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+----------------------------+
; Advanced Data - General    ;
+--------------------+-------+
; Name               ; Value ;
+--------------------+-------+
; Desired User Slack ; 0     ;
; Fit Attempts       ; 1     ;
+--------------------+-------+


+----------------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                                        ;
+--------------------------------------------------------------------------------+-------------+
; Name                                                                           ; Value       ;
+--------------------------------------------------------------------------------+-------------+
; Mid Wire Use - Fit Attempt 1                                                   ; 16          ;
; Mid Slack - Fit Attempt 1                                                      ; -11936      ;
; Internal Atom Count - Fit Attempt 1                                            ; 56          ;
; LE/ALM Count - Fit Attempt 1                                                   ; 56          ;
; LAB Count - Fit Attempt 1                                                      ; 9           ;
; Outputs per Lab - Fit Attempt 1                                                ; 6.333       ;
; Inputs per LAB - Fit Attempt 1                                                 ; 6.111       ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 1.333       ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:9         ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:8;1:1     ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:8;1:1     ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:8;1:1     ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:3;1:5;2:1 ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:3;1:5;2:1 ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:9         ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:9         ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:8;1:1     ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:3;2:6     ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:3;1:6     ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:9         ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:3;1:6     ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:5;1:4     ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 0:1;1:8     ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:7;1:2     ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:9         ;
; LEs in Chains - Fit Attempt 1                                                  ; 20          ;
; LEs in Long Chains - Fit Attempt 1                                             ; 20          ;
; LABs with Chains - Fit Attempt 1                                               ; 2           ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0           ;
; Time - Fit Attempt 1                                                           ; 0           ;
; Time in tsm_tan.dll - Fit Attempt 1                                            ; 0.016       ;
+--------------------------------------------------------------------------------+-------------+


+----------------------------------------------+
; Advanced Data - Placement                    ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Early Wire Use - Fit Attempt 1      ; 3      ;
; Early Slack - Fit Attempt 1         ; -11598 ;
; Mid Wire Use - Fit Attempt 1        ; 6      ;
; Mid Slack - Fit Attempt 1           ; -11452 ;
; Late Wire Use - Fit Attempt 1       ; 7      ;
; Late Slack - Fit Attempt 1          ; -11452 ;
; Time - Fit Attempt 1                ; 1      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.219  ;
+-------------------------------------+--------+


+----------------------------------------------+
; Advanced Data - Routing                      ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Early Slack - Fit Attempt 1         ; -10188 ;
; Early Wire Use - Fit Attempt 1      ; 4      ;
; Peak Regional Wire - Fit Attempt 1  ; 4      ;
; Mid Slack - Fit Attempt 1           ; -11854 ;
; Late Slack - Fit Attempt 1          ; -12260 ;
; Late Slack - Fit Attempt 1          ; -12260 ;
; Late Wire Use - Fit Attempt 1       ; 6      ;
; Time - Fit Attempt 1                ; 0      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.062  ;
+-------------------------------------+--------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Jun 24 23:15:22 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off bcd -c bcd
Info: Selected device EPM240T100C5 for design "bcd"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM240T100I5 is compatible
    Info: Device EPM570T100C5 is compatible
    Info: Device EPM570T100I5 is compatible
Info: No exact pin location assignment(s) for 16 pins of 16 total pins
    Info: Pin c[0] not assigned to an exact location on the device
    Info: Pin c[1] not assigned to an exact location on the device
    Info: Pin c[2] not assigned to an exact location on the device
    Info: Pin c[3] not assigned to an exact location on the device
    Info: Pin c[4] not assigned to an exact location on the device
    Info: Pin c[5] not assigned to an exact location on the device
    Info: Pin c[6] not assigned to an exact location on the device
    Info: Pin c[7] not assigned to an exact location on the device
    Info: Pin en[0] not assigned to an exact location on the device
    Info: Pin en[1] not assigned to an exact location on the device
    Info: Pin a[0] not assigned to an exact location on the device
    Info: Pin a[1] not assigned to an exact location on the device
    Info: Pin a[2] not assigned to an exact location on the device
    Info: Pin a[3] not assigned to an exact location on the device
    Info: Pin clk not assigned to an exact location on the device
    Info: Pin rst not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 14
Info: Automatically promoted signal "rst" to use Global clock in PIN 12
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 14 (unused VREF, 3.30 VCCIO, 4 input, 10 output, 0 bidirectional)
        Info: I/O standards used: LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  36 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  42 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:01
Info: Estimated most critical path is register to pin delay of 8.062 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X5_Y3; Fanout = 4; REG Node = 'en_tmp[0]'
    Info: 2: + IC(1.156 ns) + CELL(0.200 ns) = 1.356 ns; Loc. = LAB_X5_Y3; Fanout = 4; COMB Node = 'Mux0~33'
    Info: 3: + IC(0.266 ns) + CELL(0.914 ns) = 2.536 ns; Loc. = LAB_X5_Y3; Fanout = 7; COMB Node = 'Mux0~34'
    Info: 4: + IC(1.380 ns) + CELL(0.200 ns) = 4.116 ns; Loc. = LAB_X6_Y3; Fanout = 1; COMB Node = 'Mux13~15'
    Info: 5: + IC(1.624 ns) + CELL(2.322 ns) = 8.062 ns; Loc. = PIN_69; Fanout = 0; PIN Node = 'c[2]'
    Info: Total cell delay = 3.636 ns ( 45.10 % )
    Info: Total interconnect delay = 4.426 ns ( 54.90 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 3% of the available device resources. Peak interconnect usage is 3%
    Info: The peak interconnect region extends from location x0_y0 to location x8_y5
Info: Fitter routing operations ending: elapsed time is 00:00:00
Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
    Info: Pin c[0] has VCC driving its datain port
Info: Quartus II Fitter was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Jun 24 23:15:24 2008
    Info: Elapsed time: 00:00:03


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in D:/EPM240/基础实验/二进制转BCD码/bcd.fit.smsg.