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来自「CPLD的小程序集合」· 代码 · 共 415 行 · 第 1/5 页

; N/A   ; None              ; 10.521 ns       ; a[3] ; c[7] ;
; N/A   ; None              ; 10.519 ns       ; a[3] ; c[3] ;
; N/A   ; None              ; 10.496 ns       ; a[3] ; c[5] ;
; N/A   ; None              ; 9.977 ns        ; a[2] ; c[1] ;
; N/A   ; None              ; 9.971 ns        ; a[2] ; c[6] ;
; N/A   ; None              ; 9.926 ns        ; a[1] ; c[1] ;
; N/A   ; None              ; 9.908 ns        ; a[1] ; c[6] ;
; N/A   ; None              ; 9.707 ns        ; a[3] ; c[1] ;
; N/A   ; None              ; 9.701 ns        ; a[3] ; c[6] ;
; N/A   ; None              ; 9.551 ns        ; a[1] ; c[4] ;
; N/A   ; None              ; 9.409 ns        ; a[2] ; c[4] ;
; N/A   ; None              ; 9.324 ns        ; a[3] ; c[4] ;
; N/A   ; None              ; 9.293 ns        ; a[0] ; c[1] ;
; N/A   ; None              ; 9.287 ns        ; a[0] ; c[6] ;
; N/A   ; None              ; 9.227 ns        ; a[0] ; c[3] ;
; N/A   ; None              ; 9.223 ns        ; a[0] ; c[2] ;
; N/A   ; None              ; 9.215 ns        ; a[0] ; c[7] ;
; N/A   ; None              ; 9.212 ns        ; a[0] ; c[5] ;
; N/A   ; None              ; 8.700 ns        ; a[0] ; c[4] ;
+-------+-------------------+-----------------+------+------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Jun 24 23:15:28 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off bcd -c bcd
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 123.73 MHz between source register "cnt[14]" and destination register "en_tmp[1]" (period= 8.082 ns)
    Info: + Longest register to register delay is 7.373 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y4_N6; Fanout = 3; REG Node = 'cnt[14]'
        Info: 2: + IC(0.881 ns) + CELL(0.914 ns) = 1.795 ns; Loc. = LC_X6_Y4_N0; Fanout = 1; COMB Node = 'Equal0~195'
        Info: 3: + IC(2.022 ns) + CELL(0.511 ns) = 4.328 ns; Loc. = LC_X5_Y2_N3; Fanout = 4; COMB Node = 'Equal0~197'
        Info: 4: + IC(1.802 ns) + CELL(1.243 ns) = 7.373 ns; Loc. = LC_X5_Y3_N8; Fanout = 4; REG Node = 'en_tmp[1]'
        Info: Total cell delay = 2.668 ns ( 36.19 % )
        Info: Total interconnect delay = 4.705 ns ( 63.81 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 22; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y3_N8; Fanout = 4; REG Node = 'en_tmp[1]'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
        Info: - Longest clock path from clock "clk" to source register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 22; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X6_Y4_N6; Fanout = 3; REG Node = 'cnt[14]'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "clk" to destination pin "c[2]" through register "en_tmp[0]" is 12.851 ns
    Info: + Longest clock path from clock "clk" to source register is 3.348 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 22; CLK Node = 'clk'
        Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y3_N0; Fanout = 4; REG Node = 'en_tmp[0]'
        Info: Total cell delay = 2.081 ns ( 62.16 % )
        Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 9.127 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y3_N0; Fanout = 4; REG Node = 'en_tmp[0]'
        Info: 2: + IC(0.995 ns) + CELL(0.511 ns) = 1.506 ns; Loc. = LC_X5_Y3_N1; Fanout = 4; COMB Node = 'Mux0~33'
        Info: 3: + IC(0.774 ns) + CELL(0.200 ns) = 2.480 ns; Loc. = LC_X5_Y3_N4; Fanout = 7; COMB Node = 'Mux0~34'
        Info: 4: + IC(1.716 ns) + CELL(0.914 ns) = 5.110 ns; Loc. = LC_X6_Y3_N9; Fanout = 1; COMB Node = 'Mux13~15'
        Info: 5: + IC(1.695 ns) + CELL(2.322 ns) = 9.127 ns; Loc. = PIN_69; Fanout = 0; PIN Node = 'c[2]'
        Info: Total cell delay = 3.947 ns ( 43.25 % )
        Info: Total interconnect delay = 5.180 ns ( 56.75 % )
Info: Longest tpd from source pin "a[1]" to destination pin "c[2]" is 10.750 ns
    Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_81; Fanout = 4; PIN Node = 'a[1]'
    Info: 2: + IC(2.231 ns) + CELL(0.740 ns) = 4.103 ns; Loc. = LC_X5_Y3_N4; Fanout = 7; COMB Node = 'Mux0~34'
    Info: 3: + IC(1.716 ns) + CELL(0.914 ns) = 6.733 ns; Loc. = LC_X6_Y3_N9; Fanout = 1; COMB Node = 'Mux13~15'
    Info: 4: + IC(1.695 ns) + CELL(2.322 ns) = 10.750 ns; Loc. = PIN_69; Fanout = 0; PIN Node = 'c[2]'
    Info: Total cell delay = 5.108 ns ( 47.52 % )
    Info: Total interconnect delay = 5.642 ns ( 52.48 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Jun 24 23:15:29 2008
    Info: Elapsed time: 00:00:01