yinyue.map.rpt

来自「CPLD的小程序集合」· RPT 代码 · 共 271 行 · 第 1/2 页

;     -- 0 input functions                    ; 0          ;
;         -- Combinational cells for routing  ; 0          ;
;                                             ;            ;
; Logic elements by mode                      ;            ;
;     -- normal mode                          ; 194        ;
;     -- arithmetic mode                      ; 42         ;
;     -- qfbk mode                            ; 0          ;
;     -- register cascade mode                ; 0          ;
;     -- synchronous clear/load mode          ; 13         ;
;     -- asynchronous clear/load mode         ; 0          ;
;                                             ;            ;
; Total registers                             ; 52         ;
; Total logic cells in carry chains           ; 45         ;
; I/O pins                                    ; 2          ;
; Maximum fan-out node                        ; COUNTER[1] ;
; Maximum fan-out                             ; 36         ;
; Total fan-out                               ; 834        ;
; Average fan-out                             ; 3.50       ;
+---------------------------------------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                   ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |yinyue                    ; 236 (236)   ; 52           ; 0          ; 2    ; 0            ; 184 (184)    ; 5 (5)             ; 47 (47)          ; 45 (45)         ; 0 (0)      ; |yinyue             ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 52    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 13    ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 1     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; COUNTER2[0]                            ; 3       ;
; Total number of inverted registers = 1 ;         ;
+----------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 9 bits    ; 18 LEs        ; 18 LEs               ; 0 LEs                  ; Yes        ; |yinyue|COUNTER2[0]        ;
; 3:1                ; 15 bits   ; 30 LEs        ; 15 LEs               ; 15 LEs                 ; Yes        ; |yinyue|COUNTER2[1]        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+--------------------------------------------------+
; Source assignments for Top-level Entity: |yinyue ;
+----------------+-------+------+------------------+
; Assignment     ; Value ; From ; To               ;
+----------------+-------+------+------------------+
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER[5]       ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER[4]       ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER[3]       ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER[2]       ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER[1]       ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER[0]       ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER[6]       ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER[7]       ;
; POWER_UP_LEVEL ; High  ; -    ; COUNTER2[0]      ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER2[1]      ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER2[2]      ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER2[3]      ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER2[4]      ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER2[5]      ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER2[6]      ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER2[7]      ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER2[8]      ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER2[9]      ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER2[10]     ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER2[11]     ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER2[12]     ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER2[13]     ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER2[14]     ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER2[15]     ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER2[16]     ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER2[17]     ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER2[18]     ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER2[19]     ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER2[20]     ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER2[21]     ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER2[22]     ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER2[23]     ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER1[0]      ;
; POWER_UP_LEVEL ; Low   ; -    ; COUNTER1[1]      ;
+----------------+-------+------+------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Feb 12 20:10:50 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off yinyue -c yinyue
Warning: Can't analyze file -- file E:/EPM240程序/BELL/yinyue.tdf is missing
Warning: Using design file yinyue.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: YINYUE-SONG
    Info: Found entity 1: yinyue
Info: Elaborating entity "yinyue" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at yinyue.vhd(72): signal "COUNTER" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at yinyue.vhd(145): signal "DIGIT" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Duplicate registers merged to single register
    Info: Duplicate register "COUNTER1[1]" merged to single register "CLK_4MHZ"
Info: Implemented 238 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 1 output pins
    Info: Implemented 236 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
    Info: Processing ended: Thu Feb 12 20:10:56 2009
    Info: Elapsed time: 00:00:07