yinyue.fit.rpt

来自「CPLD的小程序集合」· RPT 代码 · 共 703 行 · 第 1/4 页

+----------------------------------------------+------------------------------+


+--------------------------------------------------------------------+
; Fitter Device Options                                              ;
+----------------------------------------------+---------------------+
; Option                                       ; Setting             ;
+----------------------------------------------+---------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                 ;
; Enable device-wide reset (DEV_CLRn)          ; Off                 ;
; Enable device-wide output enable (DEV_OE)    ; Off                 ;
; Enable INIT_DONE output                      ; Off                 ;
; Configuration scheme                         ; Passive Serial      ;
; Reserve all unused pins                      ; As input tri-stated ;
; Base pin-out file on sameframe device        ; Off                 ;
+----------------------------------------------+---------------------+


+----------------------------+
; Advanced Data - General    ;
+--------------------+-------+
; Name               ; Value ;
+--------------------+-------+
; Status Code        ; 0     ;
; Desired User Slack ; 0     ;
; Fit Attempts       ; 1     ;
+--------------------+-------+


+------------------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                                          ;
+--------------------------------------------------------------------------------+---------------+
; Name                                                                           ; Value         ;
+--------------------------------------------------------------------------------+---------------+
; Mid Wire Use - Fit Attempt 1                                                   ; 54            ;
; Mid Slack - Fit Attempt 1                                                      ; -15500        ;
; Internal Atom Count - Fit Attempt 1                                            ; 231           ;
; LE/ALM Count - Fit Attempt 1                                                   ; 231           ;
; LAB Count - Fit Attempt 1                                                      ; 24            ;
; Outputs per Lab - Fit Attempt 1                                                ; 5.708         ;
; Inputs per LAB - Fit Attempt 1                                                 ; 10.125        ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 0.583         ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:24          ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:21;1:3      ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:21;1:3      ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:21;1:3      ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:21;1:3      ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:21;1:3      ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:24          ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:24          ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:21;1:3      ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:11;1:12;2:1 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:11;1:11;2:2 ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:24          ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:11;1:13     ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:20;1:4      ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 1:24          ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:19;1:5      ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:24          ;
; LEs in Chains - Fit Attempt 1                                                  ; 45            ;
; LEs in Long Chains - Fit Attempt 1                                             ; 37            ;
; LABs with Chains - Fit Attempt 1                                               ; 6             ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0             ;
; Time - Fit Attempt 1                                                           ; 2             ;
; Time in tsm_tan.dll - Fit Attempt 1                                            ; 0.031         ;
+--------------------------------------------------------------------------------+---------------+


+----------------------------------------------+
; Advanced Data - Placement                    ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Auto Fit Point 2 - Fit Attempt 1    ; ff     ;
; Early Wire Use - Fit Attempt 1      ; 11     ;
; Early Slack - Fit Attempt 1         ; -20006 ;
; Auto Fit Point 3 - Fit Attempt 1    ; ff     ;
; Auto Fit Point 4 - Fit Attempt 1    ; ff     ;
; Mid Wire Use - Fit Attempt 1        ; 23     ;
; Mid Slack - Fit Attempt 1           ; -17984 ;
; Late Wire Use - Fit Attempt 1       ; 25     ;
; Late Slack - Fit Attempt 1          ; -17984 ;
; Auto Fit Point 5 - Fit Attempt 1    ; ff     ;
; Time - Fit Attempt 1                ; 0      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.093  ;
+-------------------------------------+--------+


+----------------------------------------------+
; Advanced Data - Routing                      ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Early Slack - Fit Attempt 1         ; -16797 ;
; Early Wire Use - Fit Attempt 1      ; 21     ;
; Peak Regional Wire - Fit Attempt 1  ; 19     ;
; Mid Slack - Fit Attempt 1           ; -16797 ;
; Late Slack - Fit Attempt 1          ; -16797 ;
; Late Slack - Fit Attempt 1          ; -16797 ;
; Late Wire Use - Fit Attempt 1       ; 28     ;
; Time - Fit Attempt 1                ; 1      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.202  ;
+-------------------------------------+--------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Feb 12 20:10:58 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off yinyue -c yinyue
Info: Selected device EPM240T100C5 for design "yinyue"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM240T100I5 is compatible
    Info: Device EPM570T100C5 is compatible
    Info: Device EPM570T100I5 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "CLK" to use Global clock in PIN 12
Info: Automatically promoted some destinations of signal "CLK_4MHZ" to use Global clock
    Info: Destination "CLK_4MHZ" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "CLK_4HZ" to use Global clock
    Info: Destination "CLK_4HZ" may be non-global or may not use global clock
Info: Automatically promoted signal "CARRIER" to use Global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:02
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 17.514 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X6_Y3; Fanout = 38; REG Node = 'COUNTER[1]'
    Info: 2: + IC(2.526 ns) + CELL(0.511 ns) = 3.037 ns; Loc. = LAB_X2_Y2; Fanout = 2; COMB Node = 'Equal6~58'
    Info: 3: + IC(1.558 ns) + CELL(0.740 ns) = 5.335 ns; Loc. = LAB_X3_Y3; Fanout = 1; COMB Node = 'Mux5~693'
    Info: 4: + IC(0.980 ns) + CELL(0.200 ns) = 6.515 ns; Loc. = LAB_X3_Y3; Fanout = 2; COMB Node = 'Mux5~694'
    Info: 5: + IC(0.840 ns) + CELL(0.740 ns) = 8.095 ns; Loc. = LAB_X4_Y3; Fanout = 2; COMB Node = 'Mux5~696'
    Info: 6: + IC(0.440 ns) + CELL(0.740 ns) = 9.275 ns; Loc. = LAB_X4_Y3; Fanout = 3; COMB Node = 'Mux18~510'
    Info: 7: + IC(1.360 ns) + CELL(0.914 ns) = 11.549 ns; Loc. = LAB_X5_Y2; Fanout = 4; COMB Node = 'Mux18~512'
    Info: 8: + IC(0.980 ns) + CELL(0.200 ns) = 12.729 ns; Loc. = LAB_X5_Y2; Fanout = 1; COMB Node = 'Mux18~513'
    Info: 9: + IC(1.725 ns) + CELL(0.511 ns) = 14.965 ns; Loc. = LAB_X3_Y2; Fanout = 2; COMB Node = 'Mux18~514'
    Info: 10: + IC(0.980 ns) + CELL(0.200 ns) = 16.145 ns; Loc. = LAB_X3_Y2; Fanout = 1; COMB Node = 'Mux18~515'
    Info: 11: + IC(1.089 ns) + CELL(0.280 ns) = 17.514 ns; Loc. = LAB_X3_Y2; Fanout = 4; REG Node = 'DRIVER[1]'
    Info: Total cell delay = 5.036 ns ( 28.75 % )
    Info: Total interconnect delay = 12.478 ns ( 71.25 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 18% of the available device resources. Peak interconnect usage is 18%
    Info: The peak interconnect region extends from location x0_y0 to location x8_y5
Info: Fitter routing operations ending: elapsed time is 00:00:01
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Processing ended: Thu Feb 12 20:11:02 2009
    Info: Elapsed time: 00:00:05


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in E:/EPM240程序/BELL/yinyue.fit.smsg.