yinyue.tan.qmsg

来自「CPLD的小程序集合」· QMSG 代码 · 共 11 行 · 第 1/2 页

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "CLK_4HZ " "Info: Detected ripple clock \"CLK_4HZ\" as buffer" {  } { { "yinyue.vhd" "" { Text "E:/EPM240程序/BELL/yinyue.vhd" 18 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CLK_4HZ" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "CLK_4MHZ " "Info: Detected ripple clock \"CLK_4MHZ\" as buffer" {  } { { "yinyue.vhd" "" { Text "E:/EPM240程序/BELL/yinyue.vhd" 18 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CLK_4MHZ" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "CARRIER " "Info: Detected ripple clock \"CARRIER\" as buffer" {  } { { "yinyue.vhd" "" { Text "E:/EPM240程序/BELL/yinyue.vhd" 18 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CARRIER" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register COUNTER\[1\] register DRIVER\[10\] 60.2 MHz 16.611 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 60.2 MHz between source register \"COUNTER\[1\]\" and destination register \"DRIVER\[10\]\" (period= 16.611 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.319 ns + Longest register register " "Info: + Longest register to register delay is 16.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns COUNTER\[1\] 1 REG LC_X6_Y3_N3 38 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y3_N3; Fanout = 38; REG Node = 'COUNTER\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { COUNTER[1] } "NODE_NAME" } } { "yinyue.vhd" "" { Text "E:/EPM240程序/BELL/yinyue.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.146 ns) + CELL(0.740 ns) 2.886 ns Mux5~687 2 COMB LC_X3_Y3_N6 2 " "Info: 2: + IC(2.146 ns) + CELL(0.740 ns) = 2.886 ns; Loc. = LC_X3_Y3_N6; Fanout = 2; COMB Node = 'Mux5~687'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.886 ns" { COUNTER[1] Mux5~687 } "NODE_NAME" } } { "yinyue.vhd" "" { Text "E:/EPM240程序/BELL/yinyue.vhd" 72 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.784 ns) + CELL(0.511 ns) 4.181 ns Mux5~688 3 COMB LC_X3_Y3_N0 1 " "Info: 3: + IC(0.784 ns) + CELL(0.511 ns) = 4.181 ns; Loc. = LC_X3_Y3_N0; Fanout = 1; COMB Node = 'Mux5~688'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.295 ns" { Mux5~687 Mux5~688 } "NODE_NAME" } } { "yinyue.vhd" "" { Text "E:/EPM240程序/BELL/yinyue.vhd" 72 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.875 ns) + CELL(0.200 ns) 6.256 ns Mux5~690 4 COMB LC_X4_Y3_N8 2 " "Info: 4: + IC(1.875 ns) + CELL(0.200 ns) = 6.256 ns; Loc. = LC_X4_Y3_N8; Fanout = 2; COMB Node = 'Mux5~690'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.075 ns" { Mux5~688 Mux5~690 } "NODE_NAME" } } { "yinyue.vhd" "" { Text "E:/EPM240程序/BELL/yinyue.vhd" 72 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.363 ns) + CELL(0.511 ns) 9.130 ns Mux5~695 5 COMB LC_X6_Y2_N4 13 " "Info: 5: + IC(2.363 ns) + CELL(0.511 ns) = 9.130 ns; Loc. = LC_X6_Y2_N4; Fanout = 13; COMB Node = 'Mux5~695'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.874 ns" { Mux5~690 Mux5~695 } "NODE_NAME" } } { "yinyue.vhd" "" { Text "E:/EPM240程序/BELL/yinyue.vhd" 72 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.099 ns) + CELL(0.511 ns) 12.740 ns Mux9~478 6 COMB LC_X5_Y1_N8 1 " "Info: 6: + IC(3.099 ns) + CELL(0.511 ns) = 12.740 ns; Loc. = LC_X5_Y1_N8; Fanout = 1; COMB Node = 'Mux9~478'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.610 ns" { Mux5~695 Mux9~478 } "NODE_NAME" } } { "yinyue.vhd" "" { Text "E:/EPM240程序/BELL/yinyue.vhd" 145 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.722 ns) + CELL(0.200 ns) 13.662 ns Mux9~479 7 COMB LC_X5_Y1_N3 1 " "Info: 7: + IC(0.722 ns) + CELL(0.200 ns) = 13.662 ns; Loc. = LC_X5_Y1_N3; Fanout = 1; COMB Node = 'Mux9~479'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.922 ns" { Mux9~478 Mux9~479 } "NODE_NAME" } } { "yinyue.vhd" "" { Text "E:/EPM240程序/BELL/yinyue.vhd" 145 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 14.167 ns Mux9~480 8 COMB LC_X5_Y1_N4 1 " "Info: 8: + IC(0.305 ns) + CELL(0.200 ns) = 14.167 ns; Loc. = LC_X5_Y1_N4; Fanout = 1; COMB Node = 'Mux9~480'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.505 ns" { Mux9~479 Mux9~480 } "NODE_NAME" } } { "yinyue.vhd" "" { Text "E:/EPM240程序/BELL/yinyue.vhd" 145 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.872 ns) + CELL(0.280 ns) 16.319 ns DRIVER\[10\] 9 REG LC_X4_Y2_N4 3 " "Info: 9: + IC(1.872 ns) + CELL(0.280 ns) = 16.319 ns; Loc. = LC_X4_Y2_N4; Fanout = 3; REG Node = 'DRIVER\[10\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.152 ns" { Mux9~480 DRIVER[10] } "NODE_NAME" } } { "yinyue.vhd" "" { Text "E:/EPM240程序/BELL/yinyue.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.153 ns ( 19.32 % ) " "Info: Total cell delay = 3.153 ns ( 19.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "13.166 ns ( 80.68 % ) " "Info: Total interconnect delay = 13.166 ns ( 80.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "16.319 ns" { COUNTER[1] Mux5~687 Mux5~688 Mux5~690 Mux5~695 Mux9~478 Mux9~479 Mux9~480 DRIVER[10] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "16.319 ns" { COUNTER[1] Mux5~687 Mux5~688 Mux5~690 Mux5~695 Mux9~478 Mux9~479 Mux9~480 DRIVER[10] } { 0.000ns 2.146ns 0.784ns 1.875ns 2.363ns 3.099ns 0.722ns 0.305ns 1.872ns } { 0.000ns 0.740ns 0.511ns 0.200ns 0.511ns 0.511ns 0.200ns 0.200ns 0.280ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.417 ns - Smallest " "Info: - Smallest clock skew is 0.417 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 8.605 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 8.605 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_12 27 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 27; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "yinyue.vhd" "" { Text "E:/EPM240程序/BELL/yinyue.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns CLK_4MHZ 2 REG LC_X3_Y4_N2 15 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X3_Y4_N2; Fanout = 15; REG Node = 'CLK_4MHZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.561 ns" { CLK CLK_4MHZ } "NODE_NAME" } } { "yinyue.vhd" "" { Text "E:/EPM240程序/BELL/yinyue.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.963 ns) + CELL(0.918 ns) 8.605 ns DRIVER\[10\] 3 REG LC_X4_Y2_N4 3 " "Info: 3: + IC(3.963 ns) + CELL(0.918 ns) = 8.605 ns; Loc. = LC_X4_Y2_N4; Fanout = 3; REG Node = 'DRIVER\[10\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.881 ns" { CLK_4MHZ DRIVER[10] } "NODE_NAME" } } { "yinyue.vhd" "" { Text "E:/EPM240程序/BELL/yinyue.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 39.22 % ) " "Info: Total cell delay = 3.375 ns ( 39.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.230 ns ( 60.78 % ) " "Info: Total interconnect delay = 5.230 ns ( 60.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.605 ns" { CLK CLK_4MHZ DRIVER[10] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.605 ns" { CLK CLK~combout CLK_4MHZ DRIVER[10] } { 0.000ns 0.000ns 1.267ns 3.963ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 8.188 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 8.188 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_12 27 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 27; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "yinyue.vhd" "" { Text "E:/EPM240程序/BELL/yinyue.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns CLK_4HZ 2 REG LC_X2_Y4_N9 9 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y4_N9; Fanout = 9; REG Node = 'CLK_4HZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.561 ns" { CLK CLK_4HZ } "NODE_NAME" } } { "yinyue.vhd" "" { Text "E:/EPM240程序/BELL/yinyue.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.546 ns) + CELL(0.918 ns) 8.188 ns COUNTER\[1\] 3 REG LC_X6_Y3_N3 38 " "Info: 3: + IC(3.546 ns) + CELL(0.918 ns) = 8.188 ns; Loc. = LC_X6_Y3_N3; Fanout = 38; REG Node = 'COUNTER\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.464 ns" { CLK_4HZ COUNTER[1] } "NODE_NAME" } } { "yinyue.vhd" "" { Text "E:/EPM240程序/BELL/yinyue.vhd" 66 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 41.22 % ) " "Info: Total cell delay = 3.375 ns ( 41.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.813 ns ( 58.78 % ) " "Info: Total interconnect delay = 4.813 ns ( 58.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.188 ns" { CLK CLK_4HZ COUNTER[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.188 ns" { CLK CLK~combout CLK_4HZ COUNTER[1] } { 0.000ns 0.000ns 1.267ns 3.546ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.605 ns" { CLK CLK_4MHZ DRIVER[10] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.605 ns" { CLK CLK~combout CLK_4MHZ DRIVER[10] } { 0.000ns 0.000ns 1.267ns 3.963ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.188 ns" { CLK CLK_4HZ COUNTER[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.188 ns" { CLK CLK~combout CLK_4HZ COUNTER[1] } { 0.000ns 0.000ns 1.267ns 3.546ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "yinyue.vhd" "" { Text "E:/EPM240程序/BELL/yinyue.vhd" 66 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "yinyue.vhd" "" { Text "E:/EPM240程序/BELL/yinyue.vhd" 41 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "16.319 ns" { COUNTER[1] Mux5~687 Mux5~688 Mux5~690 Mux5~695 Mux9~478 Mux9~479 Mux9~480 DRIVER[10] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "16.319 ns" { COUNTER[1] Mux5~687 Mux5~688 Mux5~690 Mux5~695 Mux9~478 Mux9~479 Mux9~480 DRIVER[10] } { 0.000ns 2.146ns 0.784ns 1.875ns 2.363ns 3.099ns 0.722ns 0.305ns 1.872ns } { 0.000ns 0.740ns 0.511ns 0.200ns 0.511ns 0.511ns 0.200ns 0.200ns 0.280ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.605 ns" { CLK CLK_4MHZ DRIVER[10] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.605 ns" { CLK CLK~combout CLK_4MHZ DRIVER[10] } { 0.000ns 0.000ns 1.267ns 3.963ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.188 ns" { CLK CLK_4HZ COUNTER[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.188 ns" { CLK CLK~combout CLK_4HZ COUNTER[1] } { 0.000ns 0.000ns 1.267ns 3.546ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK SPEAKER SPEAKER~reg0 17.365 ns register " "Info: tco from clock \"CLK\" to destination pin \"SPEAKER\" through register \"SPEAKER~reg0\" is 17.365 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 13.899 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 13.899 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_12 27 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 27; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "yinyue.vhd" "" { Text "E:/EPM240程序/BELL/yinyue.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns CLK_4MHZ 2 REG LC_X3_Y4_N2 15 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X3_Y4_N2; Fanout = 15; REG Node = 'CLK_4MHZ'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.561 ns" { CLK CLK_4MHZ } "NODE_NAME" } } { "yinyue.vhd" "" { Text "E:/EPM240程序/BELL/yinyue.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.963 ns) + CELL(1.294 ns) 8.981 ns CARRIER 3 REG LC_X3_Y1_N2 3 " "Info: 3: + IC(3.963 ns) + CELL(1.294 ns) = 8.981 ns; Loc. = LC_X3_Y1_N2; Fanout = 3; REG Node = 'CARRIER'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.257 ns" { CLK_4MHZ CARRIER } "NODE_NAME" } } { "yinyue.vhd" "" { Text "E:/EPM240程序/BELL/yinyue.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.000 ns) + CELL(0.918 ns) 13.899 ns SPEAKER~reg0 4 REG LC_X3_Y1_N8 1 " "Info: 4: + IC(4.000 ns) + CELL(0.918 ns) = 13.899 ns; Loc. = LC_X3_Y1_N8; Fanout = 1; REG Node = 'SPEAKER~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.918 ns" { CARRIER SPEAKER~reg0 } "NODE_NAME" } } { "yinyue.vhd" "" { Text "E:/EPM240程序/BELL/yinyue.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 33.59 % ) " "Info: Total cell delay = 4.669 ns ( 33.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.230 ns ( 66.41 % ) " "Info: Total interconnect delay = 9.230 ns ( 66.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "13.899 ns" { CLK CLK_4MHZ CARRIER SPEAKER~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "13.899 ns" { CLK CLK~combout CLK_4MHZ CARRIER SPEAKER~reg0 } { 0.000ns 0.000ns 1.267ns 3.963ns 4.000ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "yinyue.vhd" "" { Text "E:/EPM240程序/BELL/yinyue.vhd" 54 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.090 ns + Longest register pin " "Info: + Longest register to pin delay is 3.090 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SPEAKER~reg0 1 REG LC_X3_Y1_N8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y1_N8; Fanout = 1; REG Node = 'SPEAKER~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { SPEAKER~reg0 } "NODE_NAME" } } { "yinyue.vhd" "" { Text "E:/EPM240程序/BELL/yinyue.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.768 ns) + CELL(2.322 ns) 3.090 ns SPEAKER 2 PIN PIN_30 0 " "Info: 2: + IC(0.768 ns) + CELL(2.322 ns) = 3.090 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'SPEAKER'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.090 ns" { SPEAKER~reg0 SPEAKER } "NODE_NAME" } } { "yinyue.vhd" "" { Text "E:/EPM240程序/BELL/yinyue.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 75.15 % ) " "Info: Total cell delay = 2.322 ns ( 75.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.768 ns ( 24.85 % ) " "Info: Total interconnect delay = 0.768 ns ( 24.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.090 ns" { SPEAKER~reg0 SPEAKER } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.090 ns" { SPEAKER~reg0 SPEAKER } { 0.000ns 0.768ns } { 0.000ns 2.322ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "13.899 ns" { CLK CLK_4MHZ CARRIER SPEAKER~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "13.899 ns" { CLK CLK~combout CLK_4MHZ CARRIER SPEAKER~reg0 } { 0.000ns 0.000ns 1.267ns 3.963ns 4.000ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.090 ns" { SPEAKER~reg0 SPEAKER } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.090 ns" { SPEAKER~reg0 SPEAKER } { 0.000ns 0.768ns } { 0.000ns 2.322ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 12 20:11:07 2009 " "Info: Processing ended: Thu Feb 12 20:11:07 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}