yinyue.map.qmsg

来自「CPLD的小程序集合」· QMSG 代码 · 共 12 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Feb 12 20:10:50 2009 " "Info: Processing started: Thu Feb 12 20:10:50 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off yinyue -c yinyue " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off yinyue -c yinyue" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "E:/EPM240程序/BELL/yinyue.tdf " "Warning: Can't analyze file -- file E:/EPM240程序/BELL/yinyue.tdf is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "yinyue.vhd 2 1 " "Warning: Using design file yinyue.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 YINYUE-SONG " "Info: Found design unit 1: YINYUE-SONG" {  } { { "yinyue.vhd" "" { Text "E:/EPM240程序/BELL/yinyue.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 yinyue " "Info: Found entity 1: yinyue" {  } { { "yinyue.vhd" "" { Text "E:/EPM240程序/BELL/yinyue.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "yinyue " "Info: Elaborating entity \"yinyue\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "COUNTER yinyue.vhd(72) " "Warning (10492): VHDL Process Statement warning at yinyue.vhd(72): signal \"COUNTER\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "yinyue.vhd" "" { Text "E:/EPM240程序/BELL/yinyue.vhd" 72 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "DIGIT yinyue.vhd(145) " "Warning (10492): VHDL Process Statement warning at yinyue.vhd(145): signal \"DIGIT\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "yinyue.vhd" "" { Text "E:/EPM240程序/BELL/yinyue.vhd" 145 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "COUNTER1\[1\] CLK_4MHZ " "Info: Duplicate register \"COUNTER1\[1\]\" merged to single register \"CLK_4MHZ\"" {  } { { "yinyue.vhd" "" { Text "E:/EPM240程序/BELL/yinyue.vhd" 22 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "238 " "Info: Implemented 238 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "236 " "Info: Implemented 236 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 12 20:10:56 2009 " "Info: Processing ended: Thu Feb 12 20:10:56 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}