yinyue.tan.rpt

CPLD的小程序集合

; N/A                                     ; 102.85 MHz ( period = 9.723 ns )                    ; COUNTER2[1]  ; COUNTER2[23] ; CLK        ; CLK      ; None                        ; None                      ; 9.014 ns                ;
; N/A                                     ; 102.89 MHz ( period = 9.719 ns )                    ; COUNTER2[1]  ; COUNTER2[22] ; CLK        ; CLK      ; None                        ; None                      ; 9.010 ns                ;
; N/A                                     ; 103.17 MHz ( period = 9.693 ns )                    ; DRIVER[10]   ; DRIVER[12]   ; CLK        ; CLK      ; None                        ; None                      ; 8.984 ns                ;
; N/A                                     ; 103.17 MHz ( period = 9.693 ns )                    ; DRIVER[10]   ; DRIVER[7]    ; CLK        ; CLK      ; None                        ; None                      ; 8.984 ns                ;
; N/A                                     ; 103.17 MHz ( period = 9.693 ns )                    ; DRIVER[10]   ; DRIVER[6]    ; CLK        ; CLK      ; None                        ; None                      ; 8.984 ns                ;
; N/A                                     ; 103.17 MHz ( period = 9.693 ns )                    ; DRIVER[10]   ; DRIVER[10]   ; CLK        ; CLK      ; None                        ; None                      ; 8.984 ns                ;
; N/A                                     ; 103.17 MHz ( period = 9.693 ns )                    ; DRIVER[10]   ; DRIVER[11]   ; CLK        ; CLK      ; None                        ; None                      ; 8.984 ns                ;
; N/A                                     ; 103.17 MHz ( period = 9.693 ns )                    ; DRIVER[10]   ; DRIVER[9]    ; CLK        ; CLK      ; None                        ; None                      ; 8.984 ns                ;
; N/A                                     ; 103.17 MHz ( period = 9.693 ns )                    ; DRIVER[10]   ; DRIVER[8]    ; CLK        ; CLK      ; None                        ; None                      ; 8.984 ns                ;
; N/A                                     ; 104.01 MHz ( period = 9.614 ns )                    ; COUNTER2[3]  ; COUNTER2[15] ; CLK        ; CLK      ; None                        ; None                      ; 8.905 ns                ;
; N/A                                     ; 104.05 MHz ( period = 9.611 ns )                    ; COUNTER2[3]  ; COUNTER2[11] ; CLK        ; CLK      ; None                        ; None                      ; 8.902 ns                ;
; N/A                                     ; 104.06 MHz ( period = 9.610 ns )                    ; COUNTER2[3]  ; COUNTER2[12] ; CLK        ; CLK      ; None                        ; None                      ; 8.901 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;              ;              ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+--------------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------------+
; tco                                                                     ;
+-------+--------------+------------+--------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To      ; From Clock ;
+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 17.365 ns  ; SPEAKER~reg0 ; SPEAKER ; CLK        ;
+-------+--------------+------------+--------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Feb 12 20:11:06 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off yinyue -c yinyue
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "CLK_4HZ" as buffer
    Info: Detected ripple clock "CLK_4MHZ" as buffer
    Info: Detected ripple clock "CARRIER" as buffer
Info: Clock "CLK" has Internal fmax of 60.2 MHz between source register "COUNTER[1]" and destination register "DRIVER[10]" (period= 16.611 ns)
    Info: + Longest register to register delay is 16.319 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y3_N3; Fanout = 38; REG Node = 'COUNTER[1]'
        Info: 2: + IC(2.146 ns) + CELL(0.740 ns) = 2.886 ns; Loc. = LC_X3_Y3_N6; Fanout = 2; COMB Node = 'Mux5~687'
        Info: 3: + IC(0.784 ns) + CELL(0.511 ns) = 4.181 ns; Loc. = LC_X3_Y3_N0; Fanout = 1; COMB Node = 'Mux5~688'
        Info: 4: + IC(1.875 ns) + CELL(0.200 ns) = 6.256 ns; Loc. = LC_X4_Y3_N8; Fanout = 2; COMB Node = 'Mux5~690'
        Info: 5: + IC(2.363 ns) + CELL(0.511 ns) = 9.130 ns; Loc. = LC_X6_Y2_N4; Fanout = 13; COMB Node = 'Mux5~695'
        Info: 6: + IC(3.099 ns) + CELL(0.511 ns) = 12.740 ns; Loc. = LC_X5_Y1_N8; Fanout = 1; COMB Node = 'Mux9~478'
        Info: 7: + IC(0.722 ns) + CELL(0.200 ns) = 13.662 ns; Loc. = LC_X5_Y1_N3; Fanout = 1; COMB Node = 'Mux9~479'
        Info: 8: + IC(0.305 ns) + CELL(0.200 ns) = 14.167 ns; Loc. = LC_X5_Y1_N4; Fanout = 1; COMB Node = 'Mux9~480'
        Info: 9: + IC(1.872 ns) + CELL(0.280 ns) = 16.319 ns; Loc. = LC_X4_Y2_N4; Fanout = 3; REG Node = 'DRIVER[10]'
        Info: Total cell delay = 3.153 ns ( 19.32 % )
        Info: Total interconnect delay = 13.166 ns ( 80.68 % )
    Info: - Smallest clock skew is 0.417 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 8.605 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 27; CLK Node = 'CLK'
            Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X3_Y4_N2; Fanout = 15; REG Node = 'CLK_4MHZ'
            Info: 3: + IC(3.963 ns) + CELL(0.918 ns) = 8.605 ns; Loc. = LC_X4_Y2_N4; Fanout = 3; REG Node = 'DRIVER[10]'
            Info: Total cell delay = 3.375 ns ( 39.22 % )
            Info: Total interconnect delay = 5.230 ns ( 60.78 % )
        Info: - Longest clock path from clock "CLK" to source register is 8.188 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 27; CLK Node = 'CLK'
            Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y4_N9; Fanout = 9; REG Node = 'CLK_4HZ'
            Info: 3: + IC(3.546 ns) + CELL(0.918 ns) = 8.188 ns; Loc. = LC_X6_Y3_N3; Fanout = 38; REG Node = 'COUNTER[1]'
            Info: Total cell delay = 3.375 ns ( 41.22 % )
            Info: Total interconnect delay = 4.813 ns ( 58.78 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "CLK" to destination pin "SPEAKER" through register "SPEAKER~reg0" is 17.365 ns
    Info: + Longest clock path from clock "CLK" to source register is 13.899 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 27; CLK Node = 'CLK'
        Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X3_Y4_N2; Fanout = 15; REG Node = 'CLK_4MHZ'
        Info: 3: + IC(3.963 ns) + CELL(1.294 ns) = 8.981 ns; Loc. = LC_X3_Y1_N2; Fanout = 3; REG Node = 'CARRIER'
        Info: 4: + IC(4.000 ns) + CELL(0.918 ns) = 13.899 ns; Loc. = LC_X3_Y1_N8; Fanout = 1; REG Node = 'SPEAKER~reg0'
        Info: Total cell delay = 4.669 ns ( 33.59 % )
        Info: Total interconnect delay = 9.230 ns ( 66.41 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 3.090 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y1_N8; Fanout = 1; REG Node = 'SPEAKER~reg0'
        Info: 2: + IC(0.768 ns) + CELL(2.322 ns) = 3.090 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'SPEAKER'
        Info: Total cell delay = 2.322 ns ( 75.15 % )
        Info: Total interconnect delay = 0.768 ns ( 24.85 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Thu Feb 12 20:11:07 2009
    Info: Elapsed time: 00:00:02