+=

来自「CPLD的小程序集合」· 代码 · 共 374 行 · 第 1/4 页

; N/A                                     ; 214.87 MHz ( period = 4.654 ns )                    ; cnt[1]  ; cnt[7]   ; clk        ; clk      ; None                        ; None                      ; 3.945 ns                ;
; N/A                                     ; 214.87 MHz ( period = 4.654 ns )                    ; cnt[1]  ; cnt[8]   ; clk        ; clk      ; None                        ; None                      ; 3.945 ns                ;
; N/A                                     ; 214.87 MHz ( period = 4.654 ns )                    ; cnt[1]  ; cnt[9]   ; clk        ; clk      ; None                        ; None                      ; 3.945 ns                ;
; N/A                                     ; 214.87 MHz ( period = 4.654 ns )                    ; cnt[1]  ; cnt[10]  ; clk        ; clk      ; None                        ; None                      ; 3.945 ns                ;
; N/A                                     ; 214.87 MHz ( period = 4.654 ns )                    ; cnt[1]  ; cnt[11]  ; clk        ; clk      ; None                        ; None                      ; 3.945 ns                ;
; N/A                                     ; 214.92 MHz ( period = 4.653 ns )                    ; cnt[18] ; state[0] ; clk        ; clk      ; None                        ; None                      ; 3.944 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;         ;          ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+---------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+


+------------------------------------------------------------------+
; tco                                                              ;
+-------+--------------+------------+----------+------+------------+
; Slack ; Required tco ; Actual tco ; From     ; To   ; From Clock ;
+-------+--------------+------------+----------+------+------------+
; N/A   ; None         ; 10.189 ns  ; state[1] ; c[3] ; clk        ;
; N/A   ; None         ; 10.003 ns  ; state[2] ; c[3] ; clk        ;
; N/A   ; None         ; 9.661 ns   ; state[0] ; c[3] ; clk        ;
; N/A   ; None         ; 9.615 ns   ; state[1] ; c[2] ; clk        ;
; N/A   ; None         ; 9.532 ns   ; state[1] ; c[1] ; clk        ;
; N/A   ; None         ; 9.530 ns   ; state[1] ; c[6] ; clk        ;
; N/A   ; None         ; 9.399 ns   ; state[2] ; c[2] ; clk        ;
; N/A   ; None         ; 9.315 ns   ; state[2] ; c[1] ; clk        ;
; N/A   ; None         ; 9.306 ns   ; state[2] ; c[6] ; clk        ;
; N/A   ; None         ; 9.072 ns   ; state[0] ; c[2] ; clk        ;
; N/A   ; None         ; 9.001 ns   ; state[2] ; c[7] ; clk        ;
; N/A   ; None         ; 8.996 ns   ; state[0] ; c[6] ; clk        ;
; N/A   ; None         ; 8.996 ns   ; state[2] ; c[4] ; clk        ;
; N/A   ; None         ; 8.992 ns   ; state[2] ; c[5] ; clk        ;
; N/A   ; None         ; 8.978 ns   ; state[0] ; c[1] ; clk        ;
; N/A   ; None         ; 8.667 ns   ; state[1] ; c[7] ; clk        ;
; N/A   ; None         ; 8.662 ns   ; state[1] ; c[4] ; clk        ;
; N/A   ; None         ; 8.658 ns   ; state[1] ; c[5] ; clk        ;
; N/A   ; None         ; 8.312 ns   ; state[0] ; c[5] ; clk        ;
; N/A   ; None         ; 8.310 ns   ; state[0] ; c[7] ; clk        ;
; N/A   ; None         ; 8.308 ns   ; state[0] ; c[4] ; clk        ;
+-------+--------------+------------+----------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Jun 24 23:18:24 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off state_machine -c state_machine
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 151.52 MHz between source register "cnt[14]" and destination register "state[2]" (period= 6.6 ns)
    Info: + Longest register to register delay is 5.891 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y2_N7; Fanout = 4; REG Node = 'cnt[14]'
        Info: 2: + IC(1.285 ns) + CELL(0.914 ns) = 2.199 ns; Loc. = LC_X4_Y2_N2; Fanout = 1; COMB Node = 'Equal0~243'
        Info: 3: + IC(1.136 ns) + CELL(0.740 ns) = 4.075 ns; Loc. = LC_X3_Y2_N7; Fanout = 2; COMB Node = 'Equal0~244'
        Info: 4: + IC(0.305 ns) + CELL(0.200 ns) = 4.580 ns; Loc. = LC_X3_Y2_N8; Fanout = 2; COMB Node = 'Equal0~247'
        Info: 5: + IC(0.720 ns) + CELL(0.591 ns) = 5.891 ns; Loc. = LC_X3_Y2_N6; Fanout = 8; REG Node = 'state[2]'
        Info: Total cell delay = 2.445 ns ( 41.50 % )
        Info: Total interconnect delay = 3.446 ns ( 58.50 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 27; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X3_Y2_N6; Fanout = 8; REG Node = 'state[2]'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
        Info: - Longest clock path from clock "clk" to source register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 27; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y2_N7; Fanout = 4; REG Node = 'cnt[14]'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "clk" to destination pin "c[3]" through register "state[1]" is 10.189 ns
    Info: + Longest clock path from clock "clk" to source register is 3.348 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 27; CLK Node = 'clk'
        Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X3_Y2_N9; Fanout = 9; REG Node = 'state[1]'
        Info: Total cell delay = 2.081 ns ( 62.16 % )
        Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 6.465 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y2_N9; Fanout = 9; REG Node = 'state[1]'
        Info: 2: + IC(1.415 ns) + CELL(0.740 ns) = 2.155 ns; Loc. = LC_X2_Y2_N7; Fanout = 1; COMB Node = 'Mux6~19'
        Info: 3: + IC(1.988 ns) + CELL(2.322 ns) = 6.465 ns; Loc. = PIN_6; Fanout = 0; PIN Node = 'c[3]'
        Info: Total cell delay = 3.062 ns ( 47.36 % )
        Info: Total interconnect delay = 3.403 ns ( 52.64 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Jun 24 23:18:24 2008
    Info: Elapsed time: 00:00:01