lcdʦ

CPLD的小程序集合

; 16                                           ; 1                            ;
+----------------------------------------------+------------------------------+


+--------------------------------------------------------------------+
; Fitter Device Options                                              ;
+----------------------------------------------+---------------------+
; Option                                       ; Setting             ;
+----------------------------------------------+---------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                 ;
; Enable device-wide reset (DEV_CLRn)          ; Off                 ;
; Enable device-wide output enable (DEV_OE)    ; Off                 ;
; Enable INIT_DONE output                      ; Off                 ;
; Configuration scheme                         ; Passive Serial      ;
; Reserve all unused pins                      ; As input tri-stated ;
; Base pin-out file on sameframe device        ; Off                 ;
+----------------------------------------------+---------------------+


+----------------------------+
; Advanced Data - General    ;
+--------------------+-------+
; Name               ; Value ;
+--------------------+-------+
; Desired User Slack ; 0     ;
; Fit Attempts       ; 1     ;
+--------------------+-------+


+---------------------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                                             ;
+--------------------------------------------------------------------------------+------------------+
; Name                                                                           ; Value            ;
+--------------------------------------------------------------------------------+------------------+
; Mid Wire Use - Fit Attempt 1                                                   ; 40               ;
; Mid Slack - Fit Attempt 1                                                      ; -33506           ;
; Internal Atom Count - Fit Attempt 1                                            ; 156              ;
; LE/ALM Count - Fit Attempt 1                                                   ; 156              ;
; LAB Count - Fit Attempt 1                                                      ; 19               ;
; Outputs per Lab - Fit Attempt 1                                                ; 5.895            ;
; Inputs per LAB - Fit Attempt 1                                                 ; 9.263            ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 0.947            ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:18;1:1         ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:17;1:2         ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:16;1:2;2:1     ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:17;1:1;2:1     ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:11;1:5;2:2;3:1 ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:11;1:6;2:1;3:1 ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:18;1:1         ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:19             ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:16;1:3         ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:11;2:6;3:2     ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:11;1:4;2:4     ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:19             ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:11;1:8         ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:15;1:4         ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 0:2;1:17         ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:17;1:2         ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:19             ;
; LEs in Chains - Fit Attempt 1                                                  ; 38               ;
; LEs in Long Chains - Fit Attempt 1                                             ; 19               ;
; LABs with Chains - Fit Attempt 1                                               ; 5                ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0                ;
; Time - Fit Attempt 1                                                           ; 2                ;
; Time in tsm_tan.dll - Fit Attempt 1                                            ; 0.016            ;
+--------------------------------------------------------------------------------+------------------+


+----------------------------------------------+
; Advanced Data - Placement                    ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Early Wire Use - Fit Attempt 1      ; 7      ;
; Early Slack - Fit Attempt 1         ; -42273 ;
; Mid Wire Use - Fit Attempt 1        ; 15     ;
; Mid Slack - Fit Attempt 1           ; -38465 ;
; Late Wire Use - Fit Attempt 1       ; 17     ;
; Late Slack - Fit Attempt 1          ; -38465 ;
; Time - Fit Attempt 1                ; 2      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.595  ;
+-------------------------------------+--------+


+----------------------------------------------+
; Advanced Data - Routing                      ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Early Slack - Fit Attempt 1         ; -33692 ;
; Early Wire Use - Fit Attempt 1      ; 13     ;
; Peak Regional Wire - Fit Attempt 1  ; 12     ;
; Mid Slack - Fit Attempt 1           ; -37947 ;
; Late Slack - Fit Attempt 1          ; -36887 ;
; Late Slack - Fit Attempt 1          ; -36887 ;
; Late Wire Use - Fit Attempt 1       ; 20     ;
; Time - Fit Attempt 1                ; 2      ;
; Time in tsm_dat.dll - Fit Attempt 1 ; 0.015  ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.502  ;
+-------------------------------------+--------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun Dec 07 14:10:08 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off lcd -c lcd
Info: Selected device EPM240T100C5 for design "lcd"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM240T100I5 is compatible
    Info: Device EPM570T100C5 is compatible
    Info: Device EPM570T100I5 is compatible
Info: No exact pin location assignment(s) for 1 pins of 14 total pins
    Info: Pin clk_out not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 12
Info: Automatically promoted some destinations of signal "clk_int" to use Global clock
    Info: Destination "clk_out" may be non-global or may not use global clock
    Info: Destination "clk_int" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "clkdiv" to use Global clock
    Info: Destination "clkdiv" may be non-global or may not use global clock
Info: Automatically promoted signal "Reset" to use Global clock
Info: Pin "Reset" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:01
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 1 (unused VREF, 3.30 VCCIO, 0 input, 1 output, 0 bidirectional)
        Info: I/O standards used: LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  36 pins available
        Info: I/O bank number 2 does not use VREF pins and has 3.30V VCCIO pins. 11 total pin(s) used --  31 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:02
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:02
Info: Estimated most critical path is register to pin delay of 19.328 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X6_Y2; Fanout = 13; REG Node = 'counter[0]'
    Info: 2: + IC(2.070 ns) + CELL(0.978 ns) = 3.048 ns; Loc. = LAB_X6_Y4; Fanout = 2; COMB Node = 'Add1~120'
    Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 3.171 ns; Loc. = LAB_X6_Y4; Fanout = 2; COMB Node = 'Add1~122'
    Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 3.294 ns; Loc. = LAB_X6_Y4; Fanout = 2; COMB Node = 'Add1~124'
    Info: 5: + IC(0.000 ns) + CELL(0.399 ns) = 3.693 ns; Loc. = LAB_X6_Y4; Fanout = 2; COMB Node = 'Add1~116'
    Info: 6: + IC(0.000 ns) + CELL(1.234 ns) = 4.927 ns; Loc. = LAB_X6_Y4; Fanout = 1; COMB Node = 'Add1~117'
    Info: 7: + IC(1.534 ns) + CELL(0.740 ns) = 7.201 ns; Loc. = LAB_X6_Y3; Fanout = 2; COMB Node = 'Add2~515'
    Info: 8: + IC(0.980 ns) + CELL(0.200 ns) = 8.381 ns; Loc. = LAB_X6_Y3; Fanout = 1; COMB Node = 'Add2~516'
    Info: 9: + IC(0.669 ns) + CELL(0.511 ns) = 9.561 ns; Loc. = LAB_X6_Y3; Fanout = 11; COMB Node = 'char_addr[4]~1237'
    Info: 10: + IC(1.534 ns) + CELL(0.740 ns) = 11.835 ns; Loc. = LAB_X5_Y4; Fanout = 1; COMB Node = 'comb~1320'
    Info: 11: + IC(0.440 ns) + CELL(0.740 ns) = 13.015 ns; Loc. = LAB_X5_Y4; Fanout = 1; COMB Node = 'comb~1321'
    Info: 12: + IC(0.980 ns) + CELL(0.200 ns) = 14.195 ns; Loc. = LAB_X5_Y4; Fanout = 1; COMB Node = 'comb~1318'
    Info: 13: + IC(0.440 ns) + CELL(0.740 ns) = 15.375 ns; Loc. = LAB_X5_Y4; Fanout = 1; COMB Node = 'comb~1319'
    Info: 14: + IC(1.631 ns) + CELL(2.322 ns) = 19.328 ns; Loc. = PIN_70; Fanout = 0; PIN Node = 'data[2]'
    Info: Total cell delay = 9.050 ns ( 46.82 % )
    Info: Total interconnect delay = 10.278 ns ( 53.18 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 11% of the available device resources. Peak interconnect usage is 11%
    Info: The peak interconnect region extends from location x0_y0 to location x8_y5
Info: Fitter routing operations ending: elapsed time is 00:00:02
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Processing ended: Sun Dec 07 14:10:21 2008
    Info: Elapsed time: 00:00:14


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in F:/G盘文件/EPM240/EPM240程序/lcd液晶显示/lcd/lcd.fit.smsg.