lcdʦ

CPLD的小程序集合

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 37.327 ns
From           : state[3]
To             : data[0]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 77.88 MHz ( period = 12.840 ns )
From           : state[7]
To             : counter[6]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : lcd_e~reg0
To             : lcd_e~reg0
From Clock     : clk
To Clock       : clk
Failed Paths   : 76

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 76

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