CPLD的小程序集合

; 11                                          ; 0                            ;
; 12                                          ; 0                            ;
; 13                                          ; 0                            ;
; 14                                          ; 3                            ;
; 15                                          ; 0                            ;
; 16                                          ; 1                            ;
; 17                                          ; 0                            ;
; 18                                          ; 0                            ;
; 19                                          ; 0                            ;
; 20                                          ; 1                            ;
+---------------------------------------------+------------------------------+


+--------------------------------------------------------------------+
; Fitter Device Options                                              ;
+----------------------------------------------+---------------------+
; Option                                       ; Setting             ;
+----------------------------------------------+---------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                 ;
; Enable device-wide reset (DEV_CLRn)          ; Off                 ;
; Enable device-wide output enable (DEV_OE)    ; Off                 ;
; Enable INIT_DONE output                      ; Off                 ;
; Configuration scheme                         ; Passive Serial      ;
; Reserve all unused pins                      ; As input tri-stated ;
; Base pin-out file on sameframe device        ; Off                 ;
+----------------------------------------------+---------------------+


+----------------------------+
; Advanced Data - General    ;
+--------------------+-------+
; Name               ; Value ;
+--------------------+-------+
; Desired User Slack ; 0     ;
; Fit Attempts       ; 1     ;
+--------------------+-------+


+--------------------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                                            ;
+--------------------------------------------------------------------------------+-----------------+
; Name                                                                           ; Value           ;
+--------------------------------------------------------------------------------+-----------------+
; Mid Wire Use - Fit Attempt 1                                                   ; 20              ;
; Mid Slack - Fit Attempt 1                                                      ; -10887          ;
; Internal Atom Count - Fit Attempt 1                                            ; 89              ;
; LE/ALM Count - Fit Attempt 1                                                   ; 89              ;
; LAB Count - Fit Attempt 1                                                      ; 11              ;
; Outputs per Lab - Fit Attempt 1                                                ; 4.636           ;
; Inputs per LAB - Fit Attempt 1                                                 ; 7.909           ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 1.273           ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:11            ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:5;1:6         ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:5;1:4;2:2     ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:5;1:4;2:2     ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:4;1:1;2:4;3:2 ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:4;1:1;2:4;3:2 ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:9;1:2         ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:11            ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:5;1:6         ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:4;2:7         ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:4;1:6;2:1     ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:11            ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:4;1:7         ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:9;1:2         ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 1:11            ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:6;1:5         ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:11            ;
; LEs in Chains - Fit Attempt 1                                                  ; 34              ;
; LEs in Long Chains - Fit Attempt 1                                             ; 34              ;
; LABs with Chains - Fit Attempt 1                                               ; 5               ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0               ;
; Time - Fit Attempt 1                                                           ; 1               ;
+--------------------------------------------------------------------------------+-----------------+


+----------------------------------------------+
; Advanced Data - Placement                    ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Early Wire Use - Fit Attempt 1      ; 3      ;
; Early Slack - Fit Attempt 1         ; -12757 ;
; Mid Wire Use - Fit Attempt 1        ; 7      ;
; Mid Slack - Fit Attempt 1           ; -12421 ;
; Late Wire Use - Fit Attempt 1       ; 8      ;
; Late Slack - Fit Attempt 1          ; -12421 ;
; Time - Fit Attempt 1                ; 1      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.248  ;
+-------------------------------------+--------+


+----------------------------------------------+
; Advanced Data - Routing                      ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Early Slack - Fit Attempt 1         ; -10904 ;
; Early Wire Use - Fit Attempt 1      ; 5      ;
; Peak Regional Wire - Fit Attempt 1  ; 5      ;
; Mid Slack - Fit Attempt 1           ; -11740 ;
; Late Slack - Fit Attempt 1          ; -11536 ;
; Late Wire Use - Fit Attempt 1       ; 8      ;
; Time - Fit Attempt 1                ; 0      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.094  ;
+-------------------------------------+--------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Feb 12 20:12:29 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off buzzer -c buzzer
Info: Selected device EPM240T100C5 for design "buzzer"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM240T100I5 is compatible
    Info: Device EPM570T100C5 is compatible
    Info: Device EPM570T100I5 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 12
Info: Automatically promoted signal "rst" to use Global clock
Info: Pin "rst" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:01
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:01
Info: Estimated most critical path is register to register delay of 12.712 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X6_Y2; Fanout = 4; REG Node = 'clk_div2[12]'
    Info: 2: + IC(1.902 ns) + CELL(0.511 ns) = 2.413 ns; Loc. = LAB_X4_Y2; Fanout = 1; COMB Node = 'Equal1~83'
    Info: 3: + IC(0.669 ns) + CELL(0.511 ns) = 3.593 ns; Loc. = LAB_X4_Y2; Fanout = 2; COMB Node = 'Equal1~84'
    Info: 4: + IC(1.069 ns) + CELL(0.511 ns) = 5.173 ns; Loc. = LAB_X3_Y2; Fanout = 4; COMB Node = 'Equal1~85'
    Info: 5: + IC(1.069 ns) + CELL(0.511 ns) = 6.753 ns; Loc. = LAB_X4_Y2; Fanout = 1; COMB Node = 'clk_div2[0]~1635'
    Info: 6: + IC(0.669 ns) + CELL(0.511 ns) = 7.933 ns; Loc. = LAB_X4_Y2; Fanout = 1; COMB Node = 'clk_div2[0]~1637'
    Info: 7: + IC(0.980 ns) + CELL(0.200 ns) = 9.113 ns; Loc. = LAB_X4_Y2; Fanout = 13; COMB Node = 'clk_div2[0]~1638'
    Info: 8: + IC(1.839 ns) + CELL(1.760 ns) = 12.712 ns; Loc. = LAB_X6_Y2; Fanout = 9; REG Node = 'clk_div2[8]'
    Info: Total cell delay = 4.515 ns ( 35.52 % )
    Info: Total interconnect delay = 8.197 ns ( 64.48 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 4% of the available device resources. Peak interconnect usage is 4%
    Info: The peak interconnect region extends from location x0_y0 to location x8_y5
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Processing ended: Thu Feb 12 20:12:31 2009
    Info: Elapsed time: 00:00:03


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in E:/EPM240程序/蜂鸣器2/buzzer.fit.smsg.