来自「CPLD的小程序集合」· 代码 · 共 356 行 · 第 1/4 页

; N/A                                     ; 94.83 MHz ( period = 10.545 ns )                    ; clk_div2[7]  ; out_bit_tmp  ; clk        ; clk      ; None                        ; None                      ; 9.836 ns                ;
; N/A                                     ; 96.84 MHz ( period = 10.326 ns )                    ; clk_div2[4]  ; out_bit_tmp  ; clk        ; clk      ; None                        ; None                      ; 9.617 ns                ;
; N/A                                     ; 98.23 MHz ( period = 10.180 ns )                    ; state[0]     ; clk_div2[8]  ; clk        ; clk      ; None                        ; None                      ; 9.471 ns                ;
; N/A                                     ; 98.23 MHz ( period = 10.180 ns )                    ; state[0]     ; clk_div2[7]  ; clk        ; clk      ; None                        ; None                      ; 9.471 ns                ;
; N/A                                     ; 98.23 MHz ( period = 10.180 ns )                    ; state[0]     ; clk_div2[6]  ; clk        ; clk      ; None                        ; None                      ; 9.471 ns                ;
; N/A                                     ; 98.23 MHz ( period = 10.180 ns )                    ; state[0]     ; clk_div2[10] ; clk        ; clk      ; None                        ; None                      ; 9.471 ns                ;
; N/A                                     ; 98.23 MHz ( period = 10.180 ns )                    ; state[0]     ; clk_div2[9]  ; clk        ; clk      ; None                        ; None                      ; 9.471 ns                ;
; N/A                                     ; 98.23 MHz ( period = 10.180 ns )                    ; state[0]     ; clk_div2[11] ; clk        ; clk      ; None                        ; None                      ; 9.471 ns                ;
; N/A                                     ; 98.23 MHz ( period = 10.180 ns )                    ; state[0]     ; clk_div2[12] ; clk        ; clk      ; None                        ; None                      ; 9.471 ns                ;
; N/A                                     ; 103.53 MHz ( period = 9.659 ns )                    ; clk_div2[10] ; out_bit_tmp  ; clk        ; clk      ; None                        ; None                      ; 8.950 ns                ;
; N/A                                     ; 103.57 MHz ( period = 9.655 ns )                    ; state[0]     ; clk_div2[5]  ; clk        ; clk      ; None                        ; None                      ; 8.946 ns                ;
; N/A                                     ; 103.57 MHz ( period = 9.655 ns )                    ; state[0]     ; clk_div2[3]  ; clk        ; clk      ; None                        ; None                      ; 8.946 ns                ;
; N/A                                     ; 103.57 MHz ( period = 9.655 ns )                    ; state[0]     ; clk_div2[0]  ; clk        ; clk      ; None                        ; None                      ; 8.946 ns                ;
; N/A                                     ; 103.57 MHz ( period = 9.655 ns )                    ; state[0]     ; clk_div2[2]  ; clk        ; clk      ; None                        ; None                      ; 8.946 ns                ;
; N/A                                     ; 103.57 MHz ( period = 9.655 ns )                    ; state[0]     ; clk_div2[1]  ; clk        ; clk      ; None                        ; None                      ; 8.946 ns                ;
; N/A                                     ; 103.57 MHz ( period = 9.655 ns )                    ; state[0]     ; clk_div2[4]  ; clk        ; clk      ; None                        ; None                      ; 8.946 ns                ;
; N/A                                     ; 108.26 MHz ( period = 9.237 ns )                    ; cnt[9]       ; state[2]     ; clk        ; clk      ; None                        ; None                      ; 8.528 ns                ;
; N/A                                     ; 109.99 MHz ( period = 9.092 ns )                    ; cnt[10]      ; state[2]     ; clk        ; clk      ; None                        ; None                      ; 8.383 ns                ;
; N/A                                     ; 110.60 MHz ( period = 9.042 ns )                    ; cnt[0]       ; state[2]     ; clk        ; clk      ; None                        ; None                      ; 8.333 ns                ;
; N/A                                     ; 111.59 MHz ( period = 8.961 ns )                    ; state[1]     ; clk_div2[9]  ; clk        ; clk      ; None                        ; None                      ; 8.252 ns                ;
; N/A                                     ; 111.59 MHz ( period = 8.961 ns )                    ; state[1]     ; clk_div2[11] ; clk        ; clk      ; None                        ; None                      ; 8.252 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;              ;              ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+--------------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+------------------------------------------------------------------------+
; tco                                                                    ;
+-------+--------------+------------+-------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From        ; To      ; From Clock ;
+-------+--------------+------------+-------------+---------+------------+
; N/A   ; None         ; 6.847 ns   ; out_bit_tmp ; out_bit ; clk        ;
+-------+--------------+------------+-------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Feb 12 20:12:36 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off buzzer -c buzzer
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 80.58 MHz between source register "clk_div2[7]" and destination register "clk_div2[8]" (period= 12.41 ns)
    Info: + Longest register to register delay is 11.701 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y2_N1; Fanout = 8; REG Node = 'clk_div2[7]'
        Info: 2: + IC(0.926 ns) + CELL(0.740 ns) = 1.666 ns; Loc. = LC_X6_Y2_N8; Fanout = 2; COMB Node = 'Equal4~70'
        Info: 3: + IC(1.149 ns) + CELL(0.740 ns) = 3.555 ns; Loc. = LC_X5_Y2_N2; Fanout = 1; COMB Node = 'Equal4~71'
        Info: 4: + IC(1.214 ns) + CELL(0.511 ns) = 5.280 ns; Loc. = LC_X4_Y2_N3; Fanout = 2; COMB Node = 'Equal4~72'
        Info: 5: + IC(0.305 ns) + CELL(0.200 ns) = 5.785 ns; Loc. = LC_X4_Y2_N4; Fanout = 1; COMB Node = 'clk_div2[0]~1636'
        Info: 6: + IC(0.769 ns) + CELL(0.511 ns) = 7.065 ns; Loc. = LC_X4_Y2_N6; Fanout = 1; COMB Node = 'clk_div2[0]~1637'
        Info: 7: + IC(0.767 ns) + CELL(0.511 ns) = 8.343 ns; Loc. = LC_X4_Y2_N9; Fanout = 13; COMB Node = 'clk_div2[0]~1638'
        Info: 8: + IC(1.598 ns) + CELL(1.760 ns) = 11.701 ns; Loc. = LC_X6_Y2_N2; Fanout = 9; REG Node = 'clk_div2[8]'
        Info: Total cell delay = 4.973 ns ( 42.50 % )
        Info: Total interconnect delay = 6.728 ns ( 57.50 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 43; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X6_Y2_N2; Fanout = 9; REG Node = 'clk_div2[8]'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
        Info: - Longest clock path from clock "clk" to source register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 43; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X6_Y2_N1; Fanout = 8; REG Node = 'clk_div2[7]'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "clk" to destination pin "out_bit" through register "out_bit_tmp" is 6.847 ns
    Info: + Longest clock path from clock "clk" to source register is 3.348 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 43; CLK Node = 'clk'
        Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X3_Y1_N8; Fanout = 5; REG Node = 'out_bit_tmp'
        Info: Total cell delay = 2.081 ns ( 62.16 % )
        Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 3.123 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y1_N8; Fanout = 5; REG Node = 'out_bit_tmp'
        Info: 2: + IC(0.801 ns) + CELL(2.322 ns) = 3.123 ns; Loc. = PIN_30; Fanout = 0; PIN Node = 'out_bit'
        Info: Total cell delay = 2.322 ns ( 74.35 % )
        Info: Total interconnect delay = 0.801 ns ( 25.65 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Feb 12 20:12:36 2009
    Info: Elapsed time: 00:00:01