decl7s.vhd

来自「CPLD的小程序集合」· VHDL 代码 · 共 39 行

--本实验。按下板上的三个key时。数码管显示得到的数据。
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DECL7S  is
PORT ( key_data  : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
       LED_BIT1  : OUT STD_LOGIC ; 
       LED_BIT2  : OUT STD_LOGIC ; 
       LED_BIT3  : OUT STD_LOGIC ; 
       LED_BIT4  : OUT STD_LOGIC ; 
       LED7      : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
       LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)  ) ; 
end DECL7S ;
 
 ARCHITECTURE behav OF DECL7S IS 
 signal led_temp: std_logic_vector(2 downto 0);
 BEGIN 
  PROCESS( key_data ) 
  BEGIN 
     LED_BIT1 <= '0';
     LED_BIT2 <= '0';
     LED_BIT3 <= '0';
     LED_BIT4 <= '0';
     LED7 <="00000000" ;
     led_temp<= key_data ;
  CASE  led_temp  IS 
   WHEN "000" =>  LED7S <= "1000000" ;    --  0
   WHEN "001" =>  LED7S <= "1111001" ;    --  1
   WHEN "010" =>  LED7S <= "0100100" ;    --  2
   WHEN "011" =>  LED7S <= "0110000" ;    --  3
   WHEN "100" =>  LED7S <= "0011001" ;    --  4
   WHEN "101" =>  LED7S <= "0010010" ;    --  5
   WHEN "110" =>  LED7S <= "0000010" ;    --  6
   WHEN "111" =>  LED7S <= "1111000" ;    --  7
   WHEN OTHERS =>  NULL ; 
   END CASE ; 
  END PROCESS ; 
 END behav;