decl7s.tan.rpt

CPLD的小程序集合

Timing Analyzer report for DECL7S
Thu Dec 04 00:06:20 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                            ;
+------------------------------+-------+---------------+-------------+-------------+----------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From        ; To       ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+-------------+----------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 8.109 ns    ; key_data[0] ; LED7S[5] ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;             ;          ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+-------------+----------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM240T100C5       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+----------------------------------------------------------------------+
; tpd                                                                  ;
+-------+-------------------+-----------------+-------------+----------+
; Slack ; Required P2P Time ; Actual P2P Time ; From        ; To       ;
+-------+-------------------+-----------------+-------------+----------+
; N/A   ; None              ; 8.109 ns        ; key_data[0] ; LED7S[5] ;
; N/A   ; None              ; 8.103 ns        ; key_data[0] ; LED7S[3] ;
; N/A   ; None              ; 8.093 ns        ; key_data[0] ; LED7S[1] ;
; N/A   ; None              ; 8.005 ns        ; key_data[0] ; LED7S[2] ;
; N/A   ; None              ; 7.979 ns        ; key_data[0] ; LED7S[4] ;
; N/A   ; None              ; 7.664 ns        ; key_data[1] ; LED7S[5] ;
; N/A   ; None              ; 7.630 ns        ; key_data[1] ; LED7S[3] ;
; N/A   ; None              ; 7.620 ns        ; key_data[1] ; LED7S[1] ;
; N/A   ; None              ; 7.532 ns        ; key_data[1] ; LED7S[2] ;
; N/A   ; None              ; 7.526 ns        ; key_data[1] ; LED7S[4] ;
; N/A   ; None              ; 7.442 ns        ; key_data[2] ; LED7S[5] ;
; N/A   ; None              ; 7.416 ns        ; key_data[2] ; LED7S[3] ;
; N/A   ; None              ; 7.407 ns        ; key_data[2] ; LED7S[1] ;
; N/A   ; None              ; 7.319 ns        ; key_data[2] ; LED7S[2] ;
; N/A   ; None              ; 7.304 ns        ; key_data[2] ; LED7S[4] ;
; N/A   ; None              ; 6.858 ns        ; key_data[0] ; LED7S[6] ;
; N/A   ; None              ; 6.858 ns        ; key_data[0] ; LED7S[0] ;
; N/A   ; None              ; 6.308 ns        ; key_data[1] ; LED7S[6] ;
; N/A   ; None              ; 6.296 ns        ; key_data[1] ; LED7S[0] ;
; N/A   ; None              ; 5.702 ns        ; key_data[2] ; LED7S[0] ;
; N/A   ; None              ; 5.700 ns        ; key_data[2] ; LED7S[6] ;
+-------+-------------------+-----------------+-------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Dec 04 00:06:20 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off DECL7S -c DECL7S
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Longest tpd from source pin "key_data[0]" to destination pin "LED7S[5]" is 8.109 ns
    Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_29; Fanout = 7; PIN Node = 'key_data[0]'
    Info: 2: + IC(2.456 ns) + CELL(0.200 ns) = 3.788 ns; Loc. = LC_X2_Y3_N2; Fanout = 1; COMB Node = 'Mux1~86'
    Info: 3: + IC(1.999 ns) + CELL(2.322 ns) = 8.109 ns; Loc. = PIN_15; Fanout = 0; PIN Node = 'LED7S[5]'
    Info: Total cell delay = 3.654 ns ( 45.06 % )
    Info: Total interconnect delay = 4.455 ns ( 54.94 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Processing ended: Thu Dec 04 00:06:20 2008
    Info: Elapsed time: 00:00:01