keyboardvhdl.tan.qmsg

CPLD的小程序集合

{ "Info" "ITDB_TH_RESULT" "DFF2 KC CLK 2.364 ns register " "Info: th for register \"DFF2\" (data pin = \"KC\", clock pin = \"CLK\") is 2.364 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 7.862 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 7.862 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_12 13 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 13; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns clkDiv\[3\] 2 REG LC_X3_Y3_N6 7 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X3_Y3_N6; Fanout = 7; REG Node = 'clkDiv\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.561 ns" { CLK clkDiv[3] } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.220 ns) + CELL(0.918 ns) 7.862 ns DFF2 3 REG LC_X2_Y3_N2 1 " "Info: 3: + IC(3.220 ns) + CELL(0.918 ns) = 7.862 ns; Loc. = LC_X2_Y3_N2; Fanout = 1; REG Node = 'DFF2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.138 ns" { clkDiv[3] DFF2 } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 42.93 % ) " "Info: Total cell delay = 3.375 ns ( 42.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.487 ns ( 57.07 % ) " "Info: Total interconnect delay = 4.487 ns ( 57.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.862 ns" { CLK clkDiv[3] DFF2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.862 ns" { CLK CLK~combout clkDiv[3] DFF2 } { 0.000ns 0.000ns 1.267ns 3.220ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.719 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.719 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns KC 1 PIN PIN_3 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_3; Fanout = 1; PIN Node = 'KC'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { KC } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.307 ns) + CELL(0.280 ns) 5.719 ns DFF2 2 REG LC_X2_Y3_N2 1 " "Info: 2: + IC(4.307 ns) + CELL(0.280 ns) = 5.719 ns; Loc. = LC_X2_Y3_N2; Fanout = 1; REG Node = 'DFF2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.587 ns" { KC DFF2 } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.412 ns ( 24.69 % ) " "Info: Total cell delay = 1.412 ns ( 24.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.307 ns ( 75.31 % ) " "Info: Total interconnect delay = 4.307 ns ( 75.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.719 ns" { KC DFF2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.719 ns" { KC KC~combout DFF2 } { 0.000ns 0.000ns 4.307ns } { 0.000ns 1.132ns 0.280ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.862 ns" { CLK clkDiv[3] DFF2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.862 ns" { CLK CLK~combout clkDiv[3] DFF2 } { 0.000ns 0.000ns 1.267ns 3.220ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.719 ns" { KC DFF2 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.719 ns" { KC KC~combout DFF2 } { 0.000ns 0.000ns 4.307ns } { 0.000ns 1.132ns 0.280ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Feb 12 00:00:48 2009 " "Info: Processing ended: Thu Feb 12 00:00:48 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}