keyboardvhdl.tan.qmsg

CPLD的小程序集合

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "CLK 1 " "Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock \"CLK\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "KDI shiftRegSig1\[10\] CLK 2.375 ns " "Info: Found hold time violation between source  pin or register \"KDI\" and destination pin or register \"shiftRegSig1\[10\]\" for clock \"CLK\" (Hold time is 2.375 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.040 ns + Largest " "Info: + Largest clock skew is 4.040 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 11.902 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 11.902 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_12 13 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 13; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns clkDiv\[3\] 2 REG LC_X3_Y3_N6 7 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X3_Y3_N6; Fanout = 7; REG Node = 'clkDiv\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.561 ns" { CLK clkDiv[3] } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.220 ns) + CELL(1.294 ns) 8.238 ns KCI 3 REG LC_X2_Y3_N4 29 " "Info: 3: + IC(3.220 ns) + CELL(1.294 ns) = 8.238 ns; Loc. = LC_X2_Y3_N4; Fanout = 29; REG Node = 'KCI'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.514 ns" { clkDiv[3] KCI } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.746 ns) + CELL(0.918 ns) 11.902 ns shiftRegSig1\[10\] 4 REG LC_X6_Y1_N6 1 " "Info: 4: + IC(2.746 ns) + CELL(0.918 ns) = 11.902 ns; Loc. = LC_X6_Y1_N6; Fanout = 1; REG Node = 'shiftRegSig1\[10\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.664 ns" { KCI shiftRegSig1[10] } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 39.23 % ) " "Info: Total cell delay = 4.669 ns ( 39.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.233 ns ( 60.77 % ) " "Info: Total interconnect delay = 7.233 ns ( 60.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.902 ns" { CLK clkDiv[3] KCI shiftRegSig1[10] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.902 ns" { CLK CLK~combout clkDiv[3] KCI shiftRegSig1[10] } { 0.000ns 0.000ns 1.267ns 3.220ns 2.746ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 7.862 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to source register is 7.862 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_12 13 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 13; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns clkDiv\[3\] 2 REG LC_X3_Y3_N6 7 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X3_Y3_N6; Fanout = 7; REG Node = 'clkDiv\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.561 ns" { CLK clkDiv[3] } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.220 ns) + CELL(0.918 ns) 7.862 ns KDI 3 REG LC_X6_Y1_N2 1 " "Info: 3: + IC(3.220 ns) + CELL(0.918 ns) = 7.862 ns; Loc. = LC_X6_Y1_N2; Fanout = 1; REG Node = 'KDI'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.138 ns" { clkDiv[3] KDI } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 42.93 % ) " "Info: Total cell delay = 3.375 ns ( 42.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.487 ns ( 57.07 % ) " "Info: Total interconnect delay = 4.487 ns ( 57.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.862 ns" { CLK clkDiv[3] KDI } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.862 ns" { CLK CLK~combout clkDiv[3] KDI } { 0.000ns 0.000ns 1.267ns 3.220ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.902 ns" { CLK clkDiv[3] KCI shiftRegSig1[10] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.902 ns" { CLK CLK~combout clkDiv[3] KCI shiftRegSig1[10] } { 0.000ns 0.000ns 1.267ns 3.220ns 2.746ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.862 ns" { CLK clkDiv[3] KDI } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.862 ns" { CLK CLK~combout clkDiv[3] KDI } { 0.000ns 0.000ns 1.267ns 3.220ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" {  } { { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.510 ns - Shortest register register " "Info: - Shortest register to register delay is 1.510 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns KDI 1 REG LC_X6_Y1_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y1_N2; Fanout = 1; REG Node = 'KDI'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { KDI } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.919 ns) + CELL(0.591 ns) 1.510 ns shiftRegSig1\[10\] 2 REG LC_X6_Y1_N6 1 " "Info: 2: + IC(0.919 ns) + CELL(0.591 ns) = 1.510 ns; Loc. = LC_X6_Y1_N6; Fanout = 1; REG Node = 'shiftRegSig1\[10\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.510 ns" { KDI shiftRegSig1[10] } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.591 ns ( 39.14 % ) " "Info: Total cell delay = 0.591 ns ( 39.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.919 ns ( 60.86 % ) " "Info: Total interconnect delay = 0.919 ns ( 60.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.510 ns" { KDI shiftRegSig1[10] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.510 ns" { KDI shiftRegSig1[10] } { 0.000ns 0.919ns } { 0.000ns 0.591ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 71 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 29 -1 0 } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 71 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.902 ns" { CLK clkDiv[3] KCI shiftRegSig1[10] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.902 ns" { CLK CLK~combout clkDiv[3] KCI shiftRegSig1[10] } { 0.000ns 0.000ns 1.267ns 3.220ns 2.746ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.862 ns" { CLK clkDiv[3] KDI } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.862 ns" { CLK CLK~combout clkDiv[3] KDI } { 0.000ns 0.000ns 1.267ns 3.220ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.510 ns" { KDI shiftRegSig1[10] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.510 ns" { KDI shiftRegSig1[10] } { 0.000ns 0.919ns } { 0.000ns 0.591ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "DFF1 KD CLK -0.907 ns register " "Info: tsu for register \"DFF1\" (data pin = \"KD\", clock pin = \"CLK\") is -0.907 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.622 ns + Longest pin register " "Info: + Longest pin to register delay is 6.622 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns KD 1 PIN PIN_4 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_4; Fanout = 1; PIN Node = 'KD'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { KD } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.210 ns) + CELL(0.280 ns) 6.622 ns DFF1 2 REG LC_X6_Y1_N9 1 " "Info: 2: + IC(5.210 ns) + CELL(0.280 ns) = 6.622 ns; Loc. = LC_X6_Y1_N9; Fanout = 1; REG Node = 'DFF1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.490 ns" { KD DFF1 } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.412 ns ( 21.32 % ) " "Info: Total cell delay = 1.412 ns ( 21.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.210 ns ( 78.68 % ) " "Info: Total interconnect delay = 5.210 ns ( 78.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.622 ns" { KD DFF1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.622 ns" { KD KD~combout DFF1 } { 0.000ns 0.000ns 5.210ns } { 0.000ns 1.132ns 0.280ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 7.862 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 7.862 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_12 13 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 13; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns clkDiv\[3\] 2 REG LC_X3_Y3_N6 7 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X3_Y3_N6; Fanout = 7; REG Node = 'clkDiv\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.561 ns" { CLK clkDiv[3] } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.220 ns) + CELL(0.918 ns) 7.862 ns DFF1 3 REG LC_X6_Y1_N9 1 " "Info: 3: + IC(3.220 ns) + CELL(0.918 ns) = 7.862 ns; Loc. = LC_X6_Y1_N9; Fanout = 1; REG Node = 'DFF1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.138 ns" { clkDiv[3] DFF1 } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 42.93 % ) " "Info: Total cell delay = 3.375 ns ( 42.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.487 ns ( 57.07 % ) " "Info: Total interconnect delay = 4.487 ns ( 57.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.862 ns" { CLK clkDiv[3] DFF1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.862 ns" { CLK CLK~combout clkDiv[3] DFF1 } { 0.000ns 0.000ns 1.267ns 3.220ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.622 ns" { KD DFF1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.622 ns" { KD KD~combout DFF1 } { 0.000ns 0.000ns 5.210ns } { 0.000ns 1.132ns 0.280ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.862 ns" { CLK clkDiv[3] DFF1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.862 ns" { CLK CLK~combout clkDiv[3] DFF1 } { 0.000ns 0.000ns 1.267ns 3.220ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK sseg\[5\] WaitReg\[3\] 26.894 ns register " "Info: tco from clock \"CLK\" to destination pin \"sseg\[5\]\" through register \"WaitReg\[3\]\" is 26.894 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 11.902 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 11.902 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_12 13 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 13; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns clkDiv\[3\] 2 REG LC_X3_Y3_N6 7 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X3_Y3_N6; Fanout = 7; REG Node = 'clkDiv\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.561 ns" { CLK clkDiv[3] } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.220 ns) + CELL(1.294 ns) 8.238 ns KCI 3 REG LC_X2_Y3_N4 29 " "Info: 3: + IC(3.220 ns) + CELL(1.294 ns) = 8.238 ns; Loc. = LC_X2_Y3_N4; Fanout = 29; REG Node = 'KCI'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.514 ns" { clkDiv[3] KCI } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.746 ns) + CELL(0.918 ns) 11.902 ns WaitReg\[3\] 4 REG LC_X6_Y2_N4 2 " "Info: 4: + IC(2.746 ns) + CELL(0.918 ns) = 11.902 ns; Loc. = LC_X6_Y2_N4; Fanout = 2; REG Node = 'WaitReg\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.664 ns" { KCI WaitReg[3] } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 39.23 % ) " "Info: Total cell delay = 4.669 ns ( 39.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.233 ns ( 60.77 % ) " "Info: Total interconnect delay = 7.233 ns ( 60.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.902 ns" { CLK clkDiv[3] KCI WaitReg[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.902 ns" { CLK CLK~combout clkDiv[3] KCI WaitReg[3] } { 0.000ns 0.000ns 1.267ns 3.220ns 2.746ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 84 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.616 ns + Longest register pin " "Info: + Longest register to pin delay is 14.616 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns WaitReg\[3\] 1 REG LC_X6_Y2_N4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y2_N4; Fanout = 2; REG Node = 'WaitReg\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { WaitReg[3] } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.200 ns) 1.500 ns MUXOUT\[3\]~39 2 COMB LC_X5_Y2_N9 15 " "Info: 2: + IC(1.300 ns) + CELL(0.200 ns) = 1.500 ns; Loc. = LC_X5_Y2_N9; Fanout = 15; COMB Node = 'MUXOUT\[3\]~39'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { WaitReg[3] MUXOUT[3]~39 } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.151 ns) + CELL(0.740 ns) 5.391 ns Equal16~246 3 COMB LC_X5_Y3_N3 4 " "Info: 3: + IC(3.151 ns) + CELL(0.740 ns) = 5.391 ns; Loc. = LC_X5_Y3_N3; Fanout = 4; COMB Node = 'Equal16~246'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.891 ns" { MUXOUT[3]~39 Equal16~246 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.732 ns) + CELL(0.511 ns) 7.634 ns sseg~1648 4 COMB LC_X7_Y3_N2 1 " "Info: 4: + IC(1.732 ns) + CELL(0.511 ns) = 7.634 ns; Loc. = LC_X7_Y3_N2; Fanout = 1; COMB Node = 'sseg~1648'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.243 ns" { Equal16~246 sseg~1648 } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.754 ns) + CELL(0.914 ns) 10.302 ns sseg~1650 5 COMB LC_X6_Y2_N0 1 " "Info: 5: + IC(1.754 ns) + CELL(0.914 ns) = 10.302 ns; Loc. = LC_X6_Y2_N0; Fanout = 1; COMB Node = 'sseg~1650'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.668 ns" { sseg~1648 sseg~1650 } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.992 ns) + CELL(2.322 ns) 14.616 ns sseg\[5\] 6 PIN PIN_78 0 " "Info: 6: + IC(1.992 ns) + CELL(2.322 ns) = 14.616 ns; Loc. = PIN_78; Fanout = 0; PIN Node = 'sseg\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.314 ns" { sseg~1650 sseg[5] } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.687 ns ( 32.07 % ) " "Info: Total cell delay = 4.687 ns ( 32.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.929 ns ( 67.93 % ) " "Info: Total interconnect delay = 9.929 ns ( 67.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.616 ns" { WaitReg[3] MUXOUT[3]~39 Equal16~246 sseg~1648 sseg~1650 sseg[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "14.616 ns" { WaitReg[3] MUXOUT[3]~39 Equal16~246 sseg~1648 sseg~1650 sseg[5] } { 0.000ns 1.300ns 3.151ns 1.732ns 1.754ns 1.992ns } { 0.000ns 0.200ns 0.740ns 0.511ns 0.914ns 2.322ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.902 ns" { CLK clkDiv[3] KCI WaitReg[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.902 ns" { CLK CLK~combout clkDiv[3] KCI WaitReg[3] } { 0.000ns 0.000ns 1.267ns 3.220ns 2.746ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "14.616 ns" { WaitReg[3] MUXOUT[3]~39 Equal16~246 sseg~1648 sseg~1650 sseg[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "14.616 ns" { WaitReg[3] MUXOUT[3]~39 Equal16~246 sseg~1648 sseg~1650 sseg[5] } { 0.000ns 1.300ns 3.151ns 1.732ns 1.754ns 1.992ns } { 0.000ns 0.200ns 0.740ns 0.511ns 0.914ns 2.322ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}