keyboardvhdl.tan.qmsg

CPLD的小程序集合

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 10 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clkDiv\[3\] " "Info: Detected ripple clock \"clkDiv\[3\]\" as buffer" {  } { { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 27 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clkDiv\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "KCI " "Info: Detected ripple clock \"KCI\" as buffer" {  } { { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 29 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "KCI" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register shiftRegSig2\[6\] register WaitReg\[2\] 71.93 MHz 13.902 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 71.93 MHz between source register \"shiftRegSig2\[6\]\" and destination register \"WaitReg\[2\]\" (period= 13.902 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.242 ns + Longest register register " "Info: + Longest register to register delay is 6.242 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns shiftRegSig2\[6\] 1 REG LC_X5_Y2_N4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y2_N4; Fanout = 2; REG Node = 'shiftRegSig2\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { shiftRegSig2[6] } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.908 ns) + CELL(0.914 ns) 1.822 ns Equal0~65 2 COMB LC_X5_Y2_N7 1 " "Info: 2: + IC(0.908 ns) + CELL(0.914 ns) = 1.822 ns; Loc. = LC_X5_Y2_N7; Fanout = 1; COMB Node = 'Equal0~65'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.822 ns" { shiftRegSig2[6] Equal0~65 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.718 ns) + CELL(0.740 ns) 3.280 ns Equal0~66 3 COMB LC_X5_Y2_N5 8 " "Info: 3: + IC(0.718 ns) + CELL(0.740 ns) = 3.280 ns; Loc. = LC_X5_Y2_N5; Fanout = 8; COMB Node = 'Equal0~66'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.458 ns" { Equal0~65 Equal0~66 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.719 ns) + CELL(1.243 ns) 6.242 ns WaitReg\[2\] 4 REG LC_X7_Y2_N9 1 " "Info: 4: + IC(1.719 ns) + CELL(1.243 ns) = 6.242 ns; Loc. = LC_X7_Y2_N9; Fanout = 1; REG Node = 'WaitReg\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { Equal0~66 WaitReg[2] } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.897 ns ( 46.41 % ) " "Info: Total cell delay = 2.897 ns ( 46.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.345 ns ( 53.59 % ) " "Info: Total interconnect delay = 3.345 ns ( 53.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.242 ns" { shiftRegSig2[6] Equal0~65 Equal0~66 WaitReg[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.242 ns" { shiftRegSig2[6] Equal0~65 Equal0~66 WaitReg[2] } { 0.000ns 0.908ns 0.718ns 1.719ns } { 0.000ns 0.914ns 0.740ns 1.243ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 11.902 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 11.902 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_12 13 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 13; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns clkDiv\[3\] 2 REG LC_X3_Y3_N6 7 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X3_Y3_N6; Fanout = 7; REG Node = 'clkDiv\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.561 ns" { CLK clkDiv[3] } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.220 ns) + CELL(1.294 ns) 8.238 ns KCI 3 REG LC_X2_Y3_N4 29 " "Info: 3: + IC(3.220 ns) + CELL(1.294 ns) = 8.238 ns; Loc. = LC_X2_Y3_N4; Fanout = 29; REG Node = 'KCI'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.514 ns" { clkDiv[3] KCI } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.746 ns) + CELL(0.918 ns) 11.902 ns WaitReg\[2\] 4 REG LC_X7_Y2_N9 1 " "Info: 4: + IC(2.746 ns) + CELL(0.918 ns) = 11.902 ns; Loc. = LC_X7_Y2_N9; Fanout = 1; REG Node = 'WaitReg\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.664 ns" { KCI WaitReg[2] } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 39.23 % ) " "Info: Total cell delay = 4.669 ns ( 39.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.233 ns ( 60.77 % ) " "Info: Total interconnect delay = 7.233 ns ( 60.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.902 ns" { CLK clkDiv[3] KCI WaitReg[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.902 ns" { CLK CLK~combout clkDiv[3] KCI WaitReg[2] } { 0.000ns 0.000ns 1.267ns 3.220ns 2.746ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 11.902 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 11.902 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns CLK 1 CLK PIN_12 13 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 13; CLK Node = 'CLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns clkDiv\[3\] 2 REG LC_X3_Y3_N6 7 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X3_Y3_N6; Fanout = 7; REG Node = 'clkDiv\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.561 ns" { CLK clkDiv[3] } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.220 ns) + CELL(1.294 ns) 8.238 ns KCI 3 REG LC_X2_Y3_N4 29 " "Info: 3: + IC(3.220 ns) + CELL(1.294 ns) = 8.238 ns; Loc. = LC_X2_Y3_N4; Fanout = 29; REG Node = 'KCI'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.514 ns" { clkDiv[3] KCI } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.746 ns) + CELL(0.918 ns) 11.902 ns shiftRegSig2\[6\] 4 REG LC_X5_Y2_N4 2 " "Info: 4: + IC(2.746 ns) + CELL(0.918 ns) = 11.902 ns; Loc. = LC_X5_Y2_N4; Fanout = 2; REG Node = 'shiftRegSig2\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.664 ns" { KCI shiftRegSig2[6] } "NODE_NAME" } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 39.23 % ) " "Info: Total cell delay = 4.669 ns ( 39.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.233 ns ( 60.77 % ) " "Info: Total interconnect delay = 7.233 ns ( 60.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.902 ns" { CLK clkDiv[3] KCI shiftRegSig2[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.902 ns" { CLK CLK~combout clkDiv[3] KCI shiftRegSig2[6] } { 0.000ns 0.000ns 1.267ns 3.220ns 2.746ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.902 ns" { CLK clkDiv[3] KCI WaitReg[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.902 ns" { CLK CLK~combout clkDiv[3] KCI WaitReg[2] } { 0.000ns 0.000ns 1.267ns 3.220ns 2.746ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.902 ns" { CLK clkDiv[3] KCI shiftRegSig2[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.902 ns" { CLK CLK~combout clkDiv[3] KCI shiftRegSig2[6] } { 0.000ns 0.000ns 1.267ns 3.220ns 2.746ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 71 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 84 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 71 -1 0 } } { "keyboardVhdl.vhd" "" { Text "E:/调试好的程序/PS_2/keyboardVhdl.vhd" 84 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.242 ns" { shiftRegSig2[6] Equal0~65 Equal0~66 WaitReg[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.242 ns" { shiftRegSig2[6] Equal0~65 Equal0~66 WaitReg[2] } { 0.000ns 0.908ns 0.718ns 1.719ns } { 0.000ns 0.914ns 0.740ns 1.243ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.902 ns" { CLK clkDiv[3] KCI WaitReg[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.902 ns" { CLK CLK~combout clkDiv[3] KCI WaitReg[2] } { 0.000ns 0.000ns 1.267ns 3.220ns 2.746ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.902 ns" { CLK clkDiv[3] KCI shiftRegSig2[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.902 ns" { CLK CLK~combout clkDiv[3] KCI shiftRegSig2[6] } { 0.000ns 0.000ns 1.267ns 3.220ns 2.746ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}