📄 keyboardvhdl.fit.rpt
字号:
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 2 ;
; 17 ; 0 ;
; 18 ; 1 ;
; 19 ; 0 ;
; 20 ; 0 ;
; 21 ; 0 ;
; 22 ; 1 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+---------------------+
; Option ; Setting ;
+----------------------------------------------+---------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; Reserve all unused pins ; As input tri-stated ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+---------------------+
+----------------------------+
; Advanced Data - General ;
+--------------------+-------+
; Name ; Value ;
+--------------------+-------+
; Status Code ; 0 ;
; Desired User Slack ; 0 ;
; Fit Attempts ; 1 ;
+--------------------+-------+
+--------------------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation ;
+--------------------------------------------------------------------------------+-----------------+
; Name ; Value ;
+--------------------------------------------------------------------------------+-----------------+
; Auto Fit Point 1 - Fit Attempt 1 ; ff ;
; Mid Wire Use - Fit Attempt 1 ; 19 ;
; Mid Slack - Fit Attempt 1 ; -23600 ;
; Internal Atom Count - Fit Attempt 1 ; 91 ;
; LE/ALM Count - Fit Attempt 1 ; 91 ;
; LAB Count - Fit Attempt 1 ; 12 ;
; Outputs per Lab - Fit Attempt 1 ; 4.667 ;
; Inputs per LAB - Fit Attempt 1 ; 7.667 ;
; Global Inputs per LAB - Fit Attempt 1 ; 1.417 ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1 ; 0:12 ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1 ; 0:9;1:3 ;
; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:9;1:3 ;
; LAB Constraint 'un-route combination' - Fit Attempt 1 ; 0:9;1:3 ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1 ; 0:5;1:4;2:3 ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1 ; 0:5;1:4;2:3 ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1 ; 0:12 ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1 ; 0:12 ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1 ; 0:9;1:3 ;
; LAB Constraint 'global control signals' - Fit Attempt 1 ; 0:3;1:2;2:5;3:2 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 0:3;1:7;2:2 ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1 ; 0:12 ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1 ; 0:3;1:9 ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1 ; 0:9;1:3 ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1 ; 0:4;1:8 ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:10;1:2 ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:12 ;
; LEs in Chains - Fit Attempt 1 ; 12 ;
; LEs in Long Chains - Fit Attempt 1 ; 12 ;
; LABs with Chains - Fit Attempt 1 ; 2 ;
; LABs with Multiple Chains - Fit Attempt 1 ; 0 ;
; Time - Fit Attempt 1 ; 0 ;
+--------------------------------------------------------------------------------+-----------------+
+----------------------------------------------+
; Advanced Data - Placement ;
+-------------------------------------+--------+
; Name ; Value ;
+-------------------------------------+--------+
; Auto Fit Point 2 - Fit Attempt 1 ; ff ;
; Early Wire Use - Fit Attempt 1 ; 4 ;
; Early Slack - Fit Attempt 1 ; -30146 ;
; Auto Fit Point 3 - Fit Attempt 1 ; ff ;
; Auto Fit Point 4 - Fit Attempt 1 ; ff ;
; Mid Wire Use - Fit Attempt 1 ; 7 ;
; Mid Slack - Fit Attempt 1 ; -26788 ;
; Late Wire Use - Fit Attempt 1 ; 8 ;
; Late Slack - Fit Attempt 1 ; -26788 ;
; Auto Fit Point 5 - Fit Attempt 1 ; ff ;
; Time - Fit Attempt 1 ; 0 ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.062 ;
+-------------------------------------+--------+
+----------------------------------------------+
; Advanced Data - Routing ;
+-------------------------------------+--------+
; Name ; Value ;
+-------------------------------------+--------+
; Early Slack - Fit Attempt 1 ; -24688 ;
; Early Wire Use - Fit Attempt 1 ; 6 ;
; Peak Regional Wire - Fit Attempt 1 ; 6 ;
; Mid Slack - Fit Attempt 1 ; -26220 ;
; Late Slack - Fit Attempt 1 ; -26220 ;
; Late Slack - Fit Attempt 1 ; -26220 ;
; Late Wire Use - Fit Attempt 1 ; 12 ;
; Time - Fit Attempt 1 ; 1 ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.140 ;
+-------------------------------------+--------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Thu Feb 12 00:00:41 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off keyboardVhdl -c keyboardVhdl
Info: Selected device EPM240T100C5 for design "keyboardVhdl"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Device EPM240T100I5 is compatible
Info: Device EPM570T100C5 is compatible
Info: Device EPM570T100I5 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "CLK" to use Global clock in PIN 12
Info: Automatically promoted signal "KCI" to use Global clock
Info: Automatically promoted some destinations of signal "clkDiv[3]" to use Global clock
Info: Destination "clkDiv[3]" may be non-global or may not use global clock
Info: Automatically promoted signal "RST" to use Global clock
Info: Pin "RST" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:01
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to pin delay of 14.312 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X6_Y2; Fanout = 2; REG Node = 'WaitReg[3]'
Info: 2: + IC(1.093 ns) + CELL(0.740 ns) = 1.833 ns; Loc. = LAB_X5_Y2; Fanout = 15; COMB Node = 'MUXOUT[3]~39'
Info: 3: + IC(1.322 ns) + CELL(0.914 ns) = 4.069 ns; Loc. = LAB_X7_Y2; Fanout = 3; COMB Node = 'Equal16~235'
Info: 4: + IC(2.077 ns) + CELL(0.200 ns) = 6.346 ns; Loc. = LAB_X6_Y3; Fanout = 2; COMB Node = 'sseg~1637'
Info: 5: + IC(0.666 ns) + CELL(0.914 ns) = 7.926 ns; Loc. = LAB_X5_Y3; Fanout = 2; COMB Node = 'sseg~1644'
Info: 6: + IC(1.763 ns) + CELL(0.511 ns) = 10.200 ns; Loc. = LAB_X6_Y2; Fanout = 1; COMB Node = 'sseg~1650'
Info: 7: + IC(1.790 ns) + CELL(2.322 ns) = 14.312 ns; Loc. = PIN_78; Fanout = 0; PIN Node = 'sseg[5]'
Info: Total cell delay = 5.601 ns ( 39.13 % )
Info: Total interconnect delay = 8.711 ns ( 60.87 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 5% of the available device resources. Peak interconnect usage is 5%
Info: The peak interconnect region extends from location x0_y0 to location x8_y5
Info: Fitter routing operations ending: elapsed time is 00:00:01
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
Info: Optimizations that may affect the design's timing were skipped
Warning: Following 2 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
Info: Pin an[2] has VCC driving its datain port
Info: Pin an[3] has VCC driving its datain port
Info: Quartus II Fitter was successful. 0 errors, 1 warning
Info: Processing ended: Thu Feb 12 00:00:43 2009
Info: Elapsed time: 00:00:03
+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in E:/调试好的程序/PS_2/keyboardVhdl.fit.smsg.
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