key0.tan.qmsg

CPLD的小程序集合

{ "Info" "ITDB_FULL_TCO_RESULT" "clk row\[2\] div_cnt\[20\] 9.791 ns register " "Info: tco from clock \"clk\" to destination pin \"row\[2\]\" through register \"div_cnt\[20\]\" is 9.791 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 25 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "key0.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/接口实验/矩阵键盘/key0/key0.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns div_cnt\[20\] 2 REG LC_X6_Y1_N9 6 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X6_Y1_N9; Fanout = 6; REG Node = 'div_cnt\[20\]'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk div_cnt[20] } "NODE_NAME" } } { "key0.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/接口实验/矩阵键盘/key0/key0.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk div_cnt[20] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout div_cnt[20] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "key0.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/接口实验/矩阵键盘/key0/key0.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.067 ns + Longest register pin " "Info: + Longest register to pin delay is 6.067 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns div_cnt\[20\] 1 REG LC_X6_Y1_N9 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y1_N9; Fanout = 6; REG Node = 'div_cnt\[20\]'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { div_cnt[20] } "NODE_NAME" } } { "key0.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/接口实验/矩阵键盘/key0/key0.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.856 ns) + CELL(0.200 ns) 2.056 ns Mux1~16 2 COMB LC_X7_Y1_N5 1 " "Info: 2: + IC(1.856 ns) + CELL(0.200 ns) = 2.056 ns; Loc. = LC_X7_Y1_N5; Fanout = 1; COMB Node = 'Mux1~16'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "2.056 ns" { div_cnt[20] Mux1~16 } "NODE_NAME" } } { "key0.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/接口实验/矩阵键盘/key0/key0.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.689 ns) + CELL(2.322 ns) 6.067 ns row\[2\] 3 PIN PIN_48 0 " "Info: 3: + IC(1.689 ns) + CELL(2.322 ns) = 6.067 ns; Loc. = PIN_48; Fanout = 0; PIN Node = 'row\[2\]'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "4.011 ns" { Mux1~16 row[2] } "NODE_NAME" } } { "key0.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/接口实验/矩阵键盘/key0/key0.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.522 ns ( 41.57 % ) " "Info: Total cell delay = 2.522 ns ( 41.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.545 ns ( 58.43 % ) " "Info: Total interconnect delay = 3.545 ns ( 58.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "6.067 ns" { div_cnt[20] Mux1~16 row[2] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "6.067 ns" { div_cnt[20] Mux1~16 row[2] } { 0.000ns 1.856ns 1.689ns } { 0.000ns 0.200ns 2.322ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk div_cnt[20] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout div_cnt[20] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "6.067 ns" { div_cnt[20] Mux1~16 row[2] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "6.067 ns" { div_cnt[20] Mux1~16 row[2] } { 0.000ns 1.856ns 1.689ns } { 0.000ns 0.200ns 2.322ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "key_code\[0\] column\[2\] clk -1.323 ns register " "Info: th for register \"key_code\[0\]\" (data pin = \"column\[2\]\", clock pin = \"clk\") is -1.323 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 25 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "key0.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/接口实验/矩阵键盘/key0/key0.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns key_code\[0\] 2 REG LC_X6_Y4_N6 8 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X6_Y4_N6; Fanout = 8; REG Node = 'key_code\[0\]'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk key_code[0] } "NODE_NAME" } } { "key0.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/接口实验/矩阵键盘/key0/key0.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk key_code[0] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout key_code[0] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "key0.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/接口实验/矩阵键盘/key0/key0.vhd" 54 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.892 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.892 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns column\[2\] 1 PIN PIN_41 2 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_41; Fanout = 2; PIN Node = 'column\[2\]'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { column[2] } "NODE_NAME" } } { "key0.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/接口实验/矩阵键盘/key0/key0.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.577 ns) + CELL(1.183 ns) 4.892 ns key_code\[0\] 2 REG LC_X6_Y4_N6 8 " "Info: 2: + IC(2.577 ns) + CELL(1.183 ns) = 4.892 ns; Loc. = LC_X6_Y4_N6; Fanout = 8; REG Node = 'key_code\[0\]'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "3.760 ns" { column[2] key_code[0] } "NODE_NAME" } } { "key0.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/接口实验/矩阵键盘/key0/key0.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.315 ns ( 47.32 % ) " "Info: Total cell delay = 2.315 ns ( 47.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.577 ns ( 52.68 % ) " "Info: Total interconnect delay = 2.577 ns ( 52.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "4.892 ns" { column[2] key_code[0] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "4.892 ns" { column[2] column[2]~combout key_code[0] } { 0.000ns 0.000ns 2.577ns } { 0.000ns 1.132ns 1.183ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk key_code[0] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout key_code[0] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "4.892 ns" { column[2] key_code[0] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "4.892 ns" { column[2] column[2]~combout key_code[0] } { 0.000ns 0.000ns 2.577ns } { 0.000ns 1.132ns 1.183ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jun 25 09:18:53 2008 " "Info: Processing ended: Wed Jun 25 09:18:53 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}