key0.tan.qmsg

CPLD的小程序集合

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "key0.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/接口实验/矩阵键盘/key0/key0.vhd" 11 -1 0 } } { "d:/altera/win/Assignment Editor.qase" "" { Assignment "d:/altera/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register div_cnt\[0\] register div_cnt\[15\] 180.31 MHz 5.546 ns Internal " "Info: Clock \"clk\" has Internal fmax of 180.31 MHz between source register \"div_cnt\[0\]\" and destination register \"div_cnt\[15\]\" (period= 5.546 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.837 ns + Longest register register " "Info: + Longest register to register delay is 4.837 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns div_cnt\[0\] 1 REG LC_X4_Y1_N0 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y1_N0; Fanout = 4; REG Node = 'div_cnt\[0\]'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { div_cnt[0] } "NODE_NAME" } } { "key0.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/接口实验/矩阵键盘/key0/key0.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.254 ns) + CELL(0.978 ns) 2.232 ns div_cnt\[1\]~154 2 COMB LC_X5_Y1_N0 2 " "Info: 2: + IC(1.254 ns) + CELL(0.978 ns) = 2.232 ns; Loc. = LC_X5_Y1_N0; Fanout = 2; COMB Node = 'div_cnt\[1\]~154'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "2.232 ns" { div_cnt[0] div_cnt[1]~154 } "NODE_NAME" } } { "key0.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/接口实验/矩阵键盘/key0/key0.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.355 ns div_cnt\[2\]~153 3 COMB LC_X5_Y1_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 2.355 ns; Loc. = LC_X5_Y1_N1; Fanout = 2; COMB Node = 'div_cnt\[2\]~153'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "0.123 ns" { div_cnt[1]~154 div_cnt[2]~153 } "NODE_NAME" } } { "key0.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/接口实验/矩阵键盘/key0/key0.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.478 ns div_cnt\[3\]~152 4 COMB LC_X5_Y1_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 2.478 ns; Loc. = LC_X5_Y1_N2; Fanout = 2; COMB Node = 'div_cnt\[3\]~152'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "0.123 ns" { div_cnt[2]~153 div_cnt[3]~152 } "NODE_NAME" } } { "key0.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/接口实验/矩阵键盘/key0/key0.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.601 ns div_cnt\[4\]~151 5 COMB LC_X5_Y1_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.123 ns) = 2.601 ns; Loc. = LC_X5_Y1_N3; Fanout = 2; COMB Node = 'div_cnt\[4\]~151'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "0.123 ns" { div_cnt[3]~152 div_cnt[4]~151 } "NODE_NAME" } } { "key0.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/接口实验/矩阵键盘/key0/key0.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.261 ns) 2.862 ns div_cnt\[5\]~150 6 COMB LC_X5_Y1_N4 6 " "Info: 6: + IC(0.000 ns) + CELL(0.261 ns) = 2.862 ns; Loc. = LC_X5_Y1_N4; Fanout = 6; COMB Node = 'div_cnt\[5\]~150'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "0.261 ns" { div_cnt[4]~151 div_cnt[5]~150 } "NODE_NAME" } } { "key0.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/接口实验/矩阵键盘/key0/key0.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.349 ns) 3.211 ns div_cnt\[10\]~145 7 COMB LC_X5_Y1_N9 6 " "Info: 7: + IC(0.000 ns) + CELL(0.349 ns) = 3.211 ns; Loc. = LC_X5_Y1_N9; Fanout = 6; COMB Node = 'div_cnt\[10\]~145'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "0.349 ns" { div_cnt[5]~150 div_cnt[10]~145 } "NODE_NAME" } } { "key0.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/接口实验/矩阵键盘/key0/key0.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.626 ns) 4.837 ns div_cnt\[15\] 8 REG LC_X6_Y1_N4 2 " "Info: 8: + IC(0.000 ns) + CELL(1.626 ns) = 4.837 ns; Loc. = LC_X6_Y1_N4; Fanout = 2; REG Node = 'div_cnt\[15\]'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "1.626 ns" { div_cnt[10]~145 div_cnt[15] } "NODE_NAME" } } { "key0.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/接口实验/矩阵键盘/key0/key0.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.583 ns ( 74.07 % ) " "Info: Total cell delay = 3.583 ns ( 74.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.254 ns ( 25.93 % ) " "Info: Total interconnect delay = 1.254 ns ( 25.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "4.837 ns" { div_cnt[0] div_cnt[1]~154 div_cnt[2]~153 div_cnt[3]~152 div_cnt[4]~151 div_cnt[5]~150 div_cnt[10]~145 div_cnt[15] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "4.837 ns" { div_cnt[0] div_cnt[1]~154 div_cnt[2]~153 div_cnt[3]~152 div_cnt[4]~151 div_cnt[5]~150 div_cnt[10]~145 div_cnt[15] } { 0.000ns 1.254ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.978ns 0.123ns 0.123ns 0.123ns 0.261ns 0.349ns 1.626ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 25 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "key0.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/接口实验/矩阵键盘/key0/key0.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns div_cnt\[15\] 2 REG LC_X6_Y1_N4 2 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X6_Y1_N4; Fanout = 2; REG Node = 'div_cnt\[15\]'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk div_cnt[15] } "NODE_NAME" } } { "key0.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/接口实验/矩阵键盘/key0/key0.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk div_cnt[15] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout div_cnt[15] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 25 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "key0.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/接口实验/矩阵键盘/key0/key0.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns div_cnt\[0\] 2 REG LC_X4_Y1_N0 4 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y1_N0; Fanout = 4; REG Node = 'div_cnt\[0\]'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk div_cnt[0] } "NODE_NAME" } } { "key0.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/接口实验/矩阵键盘/key0/key0.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk div_cnt[0] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout div_cnt[0] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk div_cnt[15] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout div_cnt[15] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk div_cnt[0] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout div_cnt[0] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "key0.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/接口实验/矩阵键盘/key0/key0.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "key0.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/接口实验/矩阵键盘/key0/key0.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "4.837 ns" { div_cnt[0] div_cnt[1]~154 div_cnt[2]~153 div_cnt[3]~152 div_cnt[4]~151 div_cnt[5]~150 div_cnt[10]~145 div_cnt[15] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "4.837 ns" { div_cnt[0] div_cnt[1]~154 div_cnt[2]~153 div_cnt[3]~152 div_cnt[4]~151 div_cnt[5]~150 div_cnt[10]~145 div_cnt[15] } { 0.000ns 1.254ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.978ns 0.123ns 0.123ns 0.123ns 0.261ns 0.349ns 1.626ns } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk div_cnt[15] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout div_cnt[15] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk div_cnt[0] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout div_cnt[0] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "key_code\[0\] column\[0\] clk 3.662 ns register " "Info: tsu for register \"key_code\[0\]\" (data pin = \"column\[0\]\", clock pin = \"clk\") is 3.662 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.677 ns + Longest pin register " "Info: + Longest pin to register delay is 6.677 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns column\[0\] 1 PIN PIN_47 3 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_47; Fanout = 3; PIN Node = 'column\[0\]'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { column[0] } "NODE_NAME" } } { "key0.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/接口实验/矩阵键盘/key0/key0.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.578 ns) + CELL(0.914 ns) 4.624 ns key_code\[1\]~394 2 COMB LC_X6_Y4_N5 4 " "Info: 2: + IC(2.578 ns) + CELL(0.914 ns) = 4.624 ns; Loc. = LC_X6_Y4_N5; Fanout = 4; COMB Node = 'key_code\[1\]~394'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "3.492 ns" { column[0] key_code[1]~394 } "NODE_NAME" } } { "key0.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/接口实验/矩阵键盘/key0/key0.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.810 ns) + CELL(1.243 ns) 6.677 ns key_code\[0\] 3 REG LC_X6_Y4_N6 8 " "Info: 3: + IC(0.810 ns) + CELL(1.243 ns) = 6.677 ns; Loc. = LC_X6_Y4_N6; Fanout = 8; REG Node = 'key_code\[0\]'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "2.053 ns" { key_code[1]~394 key_code[0] } "NODE_NAME" } } { "key0.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/接口实验/矩阵键盘/key0/key0.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.289 ns ( 49.26 % ) " "Info: Total cell delay = 3.289 ns ( 49.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.388 ns ( 50.74 % ) " "Info: Total interconnect delay = 3.388 ns ( 50.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "6.677 ns" { column[0] key_code[1]~394 key_code[0] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "6.677 ns" { column[0] column[0]~combout key_code[1]~394 key_code[0] } { 0.000ns 0.000ns 2.578ns 0.810ns } { 0.000ns 1.132ns 0.914ns 1.243ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "key0.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/接口实验/矩阵键盘/key0/key0.vhd" 54 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 25 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "key0.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/接口实验/矩阵键盘/key0/key0.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns key_code\[0\] 2 REG LC_X6_Y4_N6 8 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X6_Y4_N6; Fanout = 8; REG Node = 'key_code\[0\]'" {  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk key_code[0] } "NODE_NAME" } } { "key0.vhd" "" { Text "D:/61EDA_L124/VHDL_Development_Board_Sources/接口实验/矩阵键盘/key0/key0.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk key_code[0] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout key_code[0] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "6.677 ns" { column[0] key_code[1]~394 key_code[0] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "6.677 ns" { column[0] column[0]~combout key_code[1]~394 key_code[0] } { 0.000ns 0.000ns 2.578ns 0.810ns } { 0.000ns 1.132ns 0.914ns 1.243ns } } } { "d:/altera/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk key_code[0] } "NODE_NAME" } } { "d:/altera/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/win/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout key_code[0] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}