key0.tan.rpt

CPLD的小程序集合

; N/A   ; None         ; 8.637 ns   ; div_cnt[19] ; row[1]     ; clk        ;
; N/A   ; None         ; 8.636 ns   ; key_code[0] ; dataout[4] ; clk        ;
; N/A   ; None         ; 8.634 ns   ; key_code[0] ; dataout[5] ; clk        ;
; N/A   ; None         ; 8.634 ns   ; div_cnt[19] ; row[3]     ; clk        ;
; N/A   ; None         ; 8.569 ns   ; key_code[0] ; dataout[7] ; clk        ;
; N/A   ; None         ; 8.562 ns   ; key_code[0] ; dataout[6] ; clk        ;
; N/A   ; None         ; 8.496 ns   ; key_code[1] ; dataout[0] ; clk        ;
; N/A   ; None         ; 8.404 ns   ; key_code[2] ; dataout[2] ; clk        ;
; N/A   ; None         ; 8.403 ns   ; key_code[2] ; dataout[3] ; clk        ;
; N/A   ; None         ; 8.381 ns   ; key_code[2] ; dataout[4] ; clk        ;
; N/A   ; None         ; 8.379 ns   ; key_code[2] ; dataout[5] ; clk        ;
; N/A   ; None         ; 8.291 ns   ; key_code[3] ; dataout[2] ; clk        ;
; N/A   ; None         ; 8.290 ns   ; key_code[3] ; dataout[3] ; clk        ;
; N/A   ; None         ; 8.269 ns   ; key_code[3] ; dataout[4] ; clk        ;
; N/A   ; None         ; 8.267 ns   ; key_code[3] ; dataout[5] ; clk        ;
; N/A   ; None         ; 8.178 ns   ; key_code[2] ; dataout[7] ; clk        ;
; N/A   ; None         ; 8.172 ns   ; key_code[2] ; dataout[6] ; clk        ;
; N/A   ; None         ; 7.850 ns   ; key_code[1] ; dataout[2] ; clk        ;
; N/A   ; None         ; 7.849 ns   ; key_code[1] ; dataout[3] ; clk        ;
; N/A   ; None         ; 7.828 ns   ; key_code[1] ; dataout[4] ; clk        ;
; N/A   ; None         ; 7.826 ns   ; key_code[1] ; dataout[5] ; clk        ;
+-------+--------------+------------+-------------+------------+------------+


+------------------------------------------------------------------------------+
; th                                                                           ;
+---------------+-------------+-----------+-----------+-------------+----------+
; Minimum Slack ; Required th ; Actual th ; From      ; To          ; To Clock ;
+---------------+-------------+-----------+-----------+-------------+----------+
; N/A           ; None        ; -1.323 ns ; column[2] ; key_code[0] ; clk      ;
; N/A           ; None        ; -1.362 ns ; column[1] ; key_code[0] ; clk      ;
; N/A           ; None        ; -1.392 ns ; column[0] ; key_code[1] ; clk      ;
; N/A           ; None        ; -1.396 ns ; column[0] ; key_code[0] ; clk      ;
; N/A           ; None        ; -1.541 ns ; column[1] ; key_code[1] ; clk      ;
; N/A           ; None        ; -2.639 ns ; column[3] ; key_code[3] ; clk      ;
; N/A           ; None        ; -2.648 ns ; column[1] ; key_code[3] ; clk      ;
; N/A           ; None        ; -2.714 ns ; column[2] ; key_code[3] ; clk      ;
; N/A           ; None        ; -2.754 ns ; column[0] ; key_code[3] ; clk      ;
; N/A           ; None        ; -2.963 ns ; column[3] ; key_code[2] ; clk      ;
; N/A           ; None        ; -2.972 ns ; column[1] ; key_code[2] ; clk      ;
; N/A           ; None        ; -2.993 ns ; column[3] ; key_code[0] ; clk      ;
; N/A           ; None        ; -2.993 ns ; column[3] ; key_code[1] ; clk      ;
; N/A           ; None        ; -3.038 ns ; column[2] ; key_code[2] ; clk      ;
; N/A           ; None        ; -3.068 ns ; column[2] ; key_code[1] ; clk      ;
; N/A           ; None        ; -3.078 ns ; column[0] ; key_code[2] ; clk      ;
+---------------+-------------+-----------+-----------+-------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Wed Jun 25 09:18:52 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off key0 -c key0
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 180.31 MHz between source register "div_cnt[0]" and destination register "div_cnt[15]" (period= 5.546 ns)
    Info: + Longest register to register delay is 4.837 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y1_N0; Fanout = 4; REG Node = 'div_cnt[0]'
        Info: 2: + IC(1.254 ns) + CELL(0.978 ns) = 2.232 ns; Loc. = LC_X5_Y1_N0; Fanout = 2; COMB Node = 'div_cnt[1]~154'
        Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 2.355 ns; Loc. = LC_X5_Y1_N1; Fanout = 2; COMB Node = 'div_cnt[2]~153'
        Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 2.478 ns; Loc. = LC_X5_Y1_N2; Fanout = 2; COMB Node = 'div_cnt[3]~152'
        Info: 5: + IC(0.000 ns) + CELL(0.123 ns) = 2.601 ns; Loc. = LC_X5_Y1_N3; Fanout = 2; COMB Node = 'div_cnt[4]~151'
        Info: 6: + IC(0.000 ns) + CELL(0.261 ns) = 2.862 ns; Loc. = LC_X5_Y1_N4; Fanout = 6; COMB Node = 'div_cnt[5]~150'
        Info: 7: + IC(0.000 ns) + CELL(0.349 ns) = 3.211 ns; Loc. = LC_X5_Y1_N9; Fanout = 6; COMB Node = 'div_cnt[10]~145'
        Info: 8: + IC(0.000 ns) + CELL(1.626 ns) = 4.837 ns; Loc. = LC_X6_Y1_N4; Fanout = 2; REG Node = 'div_cnt[15]'
        Info: Total cell delay = 3.583 ns ( 74.07 % )
        Info: Total interconnect delay = 1.254 ns ( 25.93 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 25; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X6_Y1_N4; Fanout = 2; REG Node = 'div_cnt[15]'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
        Info: - Longest clock path from clock "clk" to source register is 3.348 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 25; CLK Node = 'clk'
            Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y1_N0; Fanout = 4; REG Node = 'div_cnt[0]'
            Info: Total cell delay = 2.081 ns ( 62.16 % )
            Info: Total interconnect delay = 1.267 ns ( 37.84 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro