readme.txt

TIC24xdsp信号发生器库

;*************************************************************************************
;*********************** SECTION 1: SIGNAL GENERATOR LIBRARY ************************* 
;*************************************************************************************
Thank you for trying C2000 Software Collateral. 
The software is installed in C:\TIDCS\C24\DSP_TBOX\SGEN directory.

The signal generator module repository contains SIN generator ramp generator, trapezoidal & 
profile-generator modules. The signal generator modules are implemented using modulo 
arithmetic counter (i.e. Any overflow is ignored and only the remainder is kept) to precisely 
control the frequency. The frequency of the generated signal is reciprocal of the time it takes 
for successive overflow of modulo counter, which in turn commensurate with the step value added 
to the counter. Thus by changing the step value, one can precisely control the frequency.

The step value is not directly commanded to vary the frequency, instead the modulation 
of frequency is performed using the normalized variable "freq" which is normalized to 
the maximum frequency. The maximum required frequency is predetermined based on the 
application requirement and it set by initializing the "step_max" input. Thus, the 
normalized variable "freq" allows the user to control the frequency of the signal 
between 0 to maximum frequency. This strategy is adopted for all signal generator modules. 

The following table summarizes the set of modules that are available in this library.

SIGNAL GENERATOR LIBRARY
|===============|=======================================================================|
|  Module Name	| Description						        	|
|===============|=======================================================================| 
|  SGENT_1 	| Single Channel SIN Generator (Table look-up) 		  		|
|---------------|-----------------------------------------------------------------------|
|  SGENT_2 	| Dual Channel SIN Generator (Table look-up)				|
|---------------|-----------------------------------------------------------------------|
|  SGENT_3 	| 3-phase SIN Generator (Table look-up)					|
|---------------|-----------------------------------------------------------------------|
|  SGENT_3D 	| Dual 3-phase SIN Generator (Table look-up) 				|
|---------------|-----------------------------------------------------------------------|
|  SGENTI_1 	| Single Channel SIN Generator (Table look-up and Linear Interpolation) |
|---------------|-----------------------------------------------------------------------|
|  SGENTI_2 	| Dual Channel SIN Generator (Table look-up and Linear Interpolation) 	|
|---------------|-----------------------------------------------------------------------|
|  SGENTI_3 	| 3-phase SIN Generator (Table look-up and Linear interpolation) 	|
|---------------|-----------------------------------------------------------------------|
|  SGENTI_3D 	| Dual 3-phase SIN Generator (Table look-up and Linear Interpolation)	|
|---------------|-----------------------------------------------------------------------|
|  SGENHP_1 	| High Precision SIN Generator (Table look-up and Linear Interpolation) |
|---------------|-----------------------------------------------------------------------|
|  SGENHP_2 	| High Precision SIN Generator (Table look-up and Linear Interpolation) |
|---------------|-----------------------------------------------------------------------|
|  RMPGEN 	| Ramp Generator							|
|---------------|-----------------------------------------------------------------------|
|  TZDLGEN 	| Trapezoidal generator 						|
|---------------|-----------------------------------------------------------------------|
|  PROFILE 	| Profile generator  							|
|=======================================================================================|


DOCUMENTATION:
|===============|=======================================================================|
|  DOC		| DIRECTORY LOCATION				        		|
|===============|=======================================================================| 
|  MODULE DOC	| C:\TIDCS\C24\DSP_TBOX\SGEN\DOC\SGEN_MDL.PDF		  		|
|---------------|-----------------------------------------------------------------------|
|  STB DOC	| C:\TIDCS\C24\DSP_TBOX\SGEN\DOC\SGEN_STB.PDF				|
|=======================================================================================|


;*************************************************************************************
;******************** SECTION 2: Software Test Bench (STB) *************************** 
;*************************************************************************************
To facilitate evaluation and deployment of these modules, they are made available as 
Software Test Benches (STBs) which run as code composer projects on readily available 
EVMs or eZdsp hardware platforms. 

Each STB focuses on a particular software module and shows the customer how to invoke it, 
pass variable or data to it, and how to link it into their systems. Where possible, the 
module under evaluation is made to interact with other modules such as signal generators, 
which can provide input stimulus and data-logging modules or PWM-DAC drivers to examine a 
module's response in a real-time environment. This helps customers to get a more realistic 
feel of the software module's capability and applicability. 

Shown below is the STB example of 3-channel SIN generator.
		             ___________________                   ______________
			    |                   |     x1=out1     |              |
			    |			|------o--------->|  EVMDAC      |
     gain	o---------->|			|     x2=out2     |  PWMDAC      |
     offset	o---------->|	  SGENTI_3	|------o--------->|              |
     freq	o---------->|			|     x3=out3     |  DLOG_4CH    |
                       	    |			|------o--------->|              | 
			    |___________________|                 |______________|


The idea behind the STB strategy to demonstrate the signal generator module is indeed
simple. Signal generator module is initialized to generate 50Hz signal and the outputs are
logged, sent through EVMDAC and PWMDAC1 so that the user can quickly start evaluating 
the signal generator modules by varying the module properties and observing the response.