📄 int.s
字号:
BX LR
B _INT_Data_Abort
;************************************************************************
;*
;* FUNCTION
;*
;* INT_Reserved
;*
;* DESCRIPTION
;*
;* This is a stub for the Reserved Interrupt
;*
;*
;* CALLED BY
;*
;* None
;*
;* CALLS
;*
;* None
;*
;* INPUTS
;*
;* None
;*
;* OUTPUTS
;*
;* None
;*
;* HISTORY
;*
;* NAME DATE REMARKS
;*
;*
;************************************************************************
.def _INT_Reserved
_INT_Reserved
MOV r0, lr
B _INT_Reserved
;************************************************************************
;*
;* FUNCTION
;*
;* INT_IRQ
;*
;* DESCRIPTION
;*
;* This routine is the board-specific section for
;* level 1 interrupt handling
;*
;* CALLED BY
;*
;* None
;*
;* CALLS
;*
;* TMT_Timer_Interrupt
;*
;* INPUTS
;*
;* None
;*
;*
;* OUTPUTS
;*
;* None
;*
;* HISTORY
;*
;* NAME DATE REMARKS
;*
;* B. Ronquillo 05-10-00 Created initial version 1.0
;*
;************************************************************************
.def _INT_IRQ
_INT_IRQ
; ARM Core Check
STMDB sp!, {r1}
MRS r1, SPSR
TST r1, #IRQ_BIT
LDMIA sp!, {r1}
SUBNES pc,lr,#4
STMDB sp!,{r0-r4} ; Save r0-r4 on temporary IRQ stack
SUB lr,lr,#4 ; Adjust IRQ return address
;********************************
;* Begin Hardware Specific Code *
;********************************
LDR r3, INT_CNTRL_BASE_1 ; load Interrupt Control Base
LDR r4, [r3,#INT_CNTRL_MIR] ; Get enable register value
;******************************
;* End Hardware Specific Code *
;******************************
STMDB sp!,{r4} ; Put the enable register value on the IRQ stack
MVN r4,#0 ; Start with 0xFFFFFFFF to allow nesting of interrupts
;********************************
;* Begin Hardware Specific Code *
;********************************
LDR r2, [r3,#INT_CNTRL_ITR] ; Read Pending reg
;******************************
;* End Hardware Specific Code *
;******************************
LDR r3, IRQ_Priority ; Get the Priority table address
IRQ_VECTOR_LOOP
LDR r0, [r3,#0] ; Load first vector to be checked from priority table
MOV r1, #1 ; Build mask
MOV r1, r1, LSL r0 ; Use vector number to set mask to correct bit position
TST r1, r2 ; Test if pending bit is set
BNE IRQ_VECTOR_FOUND ; If bit is set, branch to found section...
BIC r4,r4,r1 ; Clear mask bit to keep higher priority ints active
ADD r3, r3, #4 ; Move to next word in the priority table
ADR r0, Priority_End ; Load the end address for the priority table
CMP r0, r3 ; Make sure not at the end of the table (shouldn't happen!)
BNE IRQ_VECTOR_LOOP ; Continue to loop if not at the end of the table
; No bits in pending register set, restore registers and exit interrupt servicing
ADD sp,sp,#4 ; Adjust sp above IRQ enable value
LDMIA sp!,{r0-r4} ; Restore r0-r4
STMDB sp!,{lr} ; Put return address for IRQ on stack
LDMIA sp!,{pc}^ ; return to the point of the exception and restore SPSR
IRQ_VECTOR_FOUND
;********************************
;* Begin Hardware Specific Code *
;********************************
LDR r3, INT_CNTRL_BASE_1 ; load Interrupt Control Base
MVN r2, r1 ; Get the inverse of the interrupt vector
STR r2, [r3,#INT_CNTRL_ITR] ; Write a zero to the interrupt being handled
LDR r2, [r3,#INT_CNTRL_MIR] ; Read the Mask reg
ORR r4, r2, r4 ; Turn off lower priority pending bits and currently masked bits
STR r4, [r3,#INT_CNTRL_MIR] ; Disable(Mask) all lower priority interrupts and currently masked interrupts
MOV r1, #1 ; Clear the pending interrupt
STR r1, [r3,#INT_CNTRL_CONTROL_REG] ; by writing a 1 to the Control Reg
;******************************
;* End Hardware Specific Code *
;******************************
LDR r3, IRQ_Vectors ; Get IRQ vector table address
MOV r2, r0, LSL #2 ; Multiply vector by 4 to get offset into table
ADD r3, r3, r2 ; Adjust vector table address to correct offset
LDR r2, [r3,#0] ; Load branch address from vector table
MOV PC, r2 ; Jump to correct branch location based on vector table
; END: INT_IRQ
;************************************************************************
;*
;* FUNCTION
;*
;* INT_IRQ_2
;*
;* DESCRIPTION
;*
;* This routine is the board-specific section for
;* level 2 interrupt handling
;*
;* CALLED BY
;*
;* None
;*
;* CALLS
;*
;* TMT_Timer_Interrupt
;*
;* INPUTS
;*
;* None
;*
;*
;* OUTPUTS
;*
;* None
;*
;* HISTORY
;*
;* NAME DATE REMARKS
;*
;* B. Ronquillo 05-10-00 Created initial version 1.0
;*
;************************************************************************
.def _INT_IRQ_2
_INT_IRQ_2
LDMIA sp!, {r1}
; Re-enable all lower priority interrupts
LDR r2,INT_CNTRL_BASE_1 ; Get IRQ0 base register address
STR r1,[r2,#INT_CNTRL_MIR] ; Re-enable all lower priority interrupts
;********************************
;* Begin Hardware Specific Code *
;********************************
LDR r3, INT_CNTRL_BASE_2 ; load Interrupt Control Base
LDR r4, [r3,#INT_CNTRL_MIR] ; Get enable register value
;******************************
;* End Hardware Specific Code *
;******************************
STMDB sp!,{r4} ; Put the enable register value on the IRQ stack
MVN r4, #0 ; Grab a value of all FFFF for EORing
;********************************
;* Begin Hardware Specific Code *
;********************************
LDR r2, [r3,#INT_CNTRL_ITR] ; Read Pending reg
;******************************
;* End Hardware Specific Code *
;******************************
LDR r3, IRQ_Priority_2 ; Get the Priority table address
IRQ_VECTOR_LOOP_2
LDR r0, [r3,#0] ; Load first vector to be checked from priority table
SUB r0,r0,#32 ; Subtract 32 to get correct offset in IRQ2 pending register
MOV r1, #1 ; Build mask
MOV r1, r1, LSL r0 ; Use vector number to set mask to correct bit position
TST r1, r2 ; Test if pending bit is set
BNE IRQ_VECTOR_FOUND_2 ; If bit is set, branch to found section...
BIC r4,r4,r1 ; Clear the enable bit to keep higher priority ints active
ADD r3, r3, #4 ; Move to next word in the priority table
ADR r0, Priority_End_2 ; Load the end address for the priority table
CMP r0, r3 ; Make sure not at the end of the table (shouldn't happen!)
BNE IRQ_VECTOR_LOOP_2 ; Continue to loop if not at the end of the table
; No bits in pending register set, restore registers and exit interrupt servicing
ADD sp,sp,#4 ; Adjust sp above IRQ enable value
LDMIA sp!,{r0-r4} ; Restore r0-r4
STMDB sp!,{lr} ; Put return address for IRQ on stack
LDMIA sp!,{pc}^ ; return to the point of the exception and restore SPSR
IRQ_VECTOR_FOUND_2
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