init.c

sst flash的读写程序的编写 完整教程和实例程序和几个实用小工具

/* 
 * Purpose:		Initialize ColdFire 5307
 *
 */

#define IMMaddr	0x10000000
#define SDRAMaddr 0x00000000
#define SDRAMsize 0x00800000		//8M
#define SRAMaddr 0x00800000
#define SRAMsize (4 * 1024)		//4K
#define EXT_SRAMaddr 0xFE400000	
#define EXT_SRAMsize (128 * 1024)	//128K


#include "mcf5307.h" 
void
mcf5307_sim_init (MCF5307_IMM *imm)
{
	
        /************************************************************************/
        /*                                                                      */
        /*  This routine executed upon reset to initialize MCF5307              */
        /*  peripherals, except Chip Selects and DRAM.  An initial stack must   */
        /*  have been setup in the internal SRAM in order for this routine to 	*/
	/*  work.      								*/
        /*                                                                      */
        /************************************************************************/

        /************************************************************************/
        /*  SIM                                                                 */
        /************************************************************************/
        imm->sim.SYPCR = 0;   /*  Disable the Software Watchdog                         */
        imm->sim.PAR = 0xff00;     /*  Set all Par Ports to General I/O   ,low as gen .io.                   */
        
        imm->sim.IRQPAR = 0;  /*  IRQ1,3,5 are Internal Interrupts 1,3,5, respectively  */
              
        imm->sim.PLLCR = 0x80;   /*  Disable CPU STOP Instruction                          */
        imm->sim.MPARK = 0;   /*  Disable external visibility of internal bus           */
        imm->sim.IPR = ~0;    /*  Clear all pending interrupts                          */
        imm->sim.IMR = ( 0    /*  Mask all interrupt sources                            */
                | MCF5307_SIM_IMR_DMA3
                | MCF5307_SIM_IMR_DMA2
                | MCF5307_SIM_IMR_DMA1
                | MCF5307_SIM_IMR_DMA0
                | MCF5307_SIM_IMR_UART2
                | MCF5307_SIM_IMR_UART1
                | MCF5307_SIM_IMR_TIMER2
                | MCF5307_SIM_IMR_TIMER1
                | MCF5307_SIM_IMR_SWT
                | MCF5307_SIM_IMR_EINT7
                | MCF5307_SIM_IMR_EINT6
                | MCF5307_SIM_IMR_EINT5
                | MCF5307_SIM_IMR_EINT4
                | MCF5307_SIM_IMR_EINT3
                | MCF5307_SIM_IMR_EINT2
                | MCF5307_SIM_IMR_EINT1 ) ;
        imm->sim.AVCR = (0
		| MCF5307_SIM_AVCR_AVEC7 
		| MCF5307_SIM_AVCR_AVEC6
		| MCF5307_SIM_AVCR_AVEC5
		| MCF5307_SIM_AVCR_AVEC4
		| MCF5307_SIM_AVCR_AVEC3
		| MCF5307_SIM_AVCR_AVEC2
		| MCF5307_SIM_AVCR_AVEC1
                | MCF5307_SIM_AVCR_BLK );  /*  Block address strobe for external AVEC   */
        /*  Setup Interrupt Source Vectors               */
        /*      All interrupts are autovectored          */
        /*      The levels are set to the numbers shown  */
        /*      The priorities exceed the type shown     */
        imm->sim.ICR0 = ( 0                     /* Software Watchdog */
                | MCF5307_SIM_ICR_AVEC
                | MCF5307_SIM_ICR_IL(7)
                | MCF5307_SIM_ICR_IP_EXT ) ;
        imm->sim.ICR1 = ( 0
                | MCF5307_SIM_ICR_AVEC          /* Timer 1 */
                | MCF5307_SIM_ICR_IL(5)
                | MCF5307_SIM_ICR_IP_EXT
                | MCF5307_SIM_ICR_IP_INT ) ;
	imm->sim.ICR2 = ( 0
                | MCF5307_SIM_ICR_AVEC          /* Timer 2 */
                | MCF5307_SIM_ICR_IL(5)
                | MCF5307_SIM_ICR_IP_INT ) ;
	imm->sim.ICR3 = ( 0
                | MCF5307_SIM_ICR_AVEC          /* MBUS */
                | MCF5307_SIM_ICR_IL(3) ) ;
        imm->sim.ICR4 = ( 0
                | MCF5307_SIM_ICR_AVEC          /* UART 1 */
                | MCF5307_SIM_ICR_IL(3)
                | MCF5307_SIM_ICR_IP_EXT ) ;
        imm->sim.ICR5 = ( 0
                | MCF5307_SIM_ICR_AVEC          /* UART 2 */
                | MCF5307_SIM_ICR_IL(3)
                | MCF5307_SIM_ICR_IP_INT ) ;
        imm->sim.ICR6 = ( 0
                | MCF5307_SIM_ICR_AVEC          /* DMA 0 */
                | MCF5307_SIM_ICR_IL(2) ) ;
        imm->sim.ICR7 = ( 0
                | MCF5307_SIM_ICR_AVEC          /* DMA 1 */
                | MCF5307_SIM_ICR_IL(2)
                | MCF5307_SIM_ICR_IP_INT ) ;
        imm->sim.ICR8 = ( 0
                | MCF5307_SIM_ICR_AVEC          /* DMA 2 */
                | MCF5307_SIM_ICR_IL(2)
                | MCF5307_SIM_ICR_IP_EXT ) ;
        imm->sim.ICR9 = ( 0
                | MCF5307_SIM_ICR_AVEC          /* DMA 3 */
                | MCF5307_SIM_ICR_IL(2)
                | MCF5307_SIM_ICR_IP_EXT
                | MCF5307_SIM_ICR_IP_INT ) ;
        imm->sim.ICR10 = ( 0
                | MCF5307_SIM_ICR_AVEC          /* unused */
                | MCF5307_SIM_ICR_IL(1) ) ;
        imm->sim.ICR11 = ( 0
                | MCF5307_SIM_ICR_AVEC          /* unused */
                | MCF5307_SIM_ICR_IL(1)
                | MCF5307_SIM_ICR_IP_EXT ) ;
}
 
void
mcf5307_timer_init (MCF5307_IMM *imm)
{
        /************************************************************************/
        /*  Timers                                                              */
        /************************************************************************/
 
        imm->timer.TMR1 = 0 ;   /* Stop clock and disable timer */
        imm->timer.TMR2 = 0 ;   /* Stop clock and disable timer */
}
 
void
mcf5307_pport_init (MCF5307_IMM *imm)
{
        /************************************************************************/
        /*  Parallel Port                                                       */
        /************************************************************************/
 
        imm->parallel_port.PADDR = 0xFF;   /* Init PADDR to all output*/
}
 
void
mcf5307_mbus_init (MCF5307_IMM *imm)
{
        /************************************************************************/
	/*  MBUS								*/
        /************************************************************************/

	imm->mbus.MBCR = 0;     /* Disable MBUS */
}
 
void
mcf5307_dma_init (MCF5307_IMM *imm)
{
        /************************************************************************/
        /*  DMA                                                                 */
        /************************************************************************/
 
        imm->dma.DCR0 = 0;      /* Disable DMA 0 */
        imm->dma.DCR1 = 0;      /* Disable DMA 1 */
        imm->dma.DCR2 = 0;      /* Disable DMA 2 */
        imm->dma.DCR3 = 0;      /* Disable DMA 3 */
}



void
mcf5307_uart_init(MCF5307_IMM *imm)
{
	/************************************************************************/
	/*									*/
	/*  This routine initializes UART 1 and UART 2 on the board.		*/
	/*									*/
	/************************************************************************/

	/************************************************************************/
	/*  UART 1								*/
	/************************************************************************/

	imm->uart1.UCR1 = MCF5307_UART_UCR_RESET_TX;	/* Transmitter Reset	*/
	imm->uart1.UCR1 = MCF5307_UART_UCR_RESET_RX;	/* Receiver Reset	*/
	imm->uart1.UCR1 = MCF5307_UART_UCR_RESET_MR;	/* Mode Register Reset	*/

	imm->uart1.UMR11_UMR21 = ( 0
		/* RTS is automatically negated	*/
		/* Interrupts when FIFO is full	*/
		/* Error occurs in BLOCK mode	*/
		| MCF5307_UART_UMR1_PM_NONE		/* No parity	*/
		| MCF5307_UART_UMR1_BC_8		/* 8 bits per character	*/
		) ;
	imm->uart1.UMR11_UMR21 = ( 0
		| MCF5307_UART_UMR2_CM_NORMAL		/* No echo or loopback	*/
		/* Transmitter RTS has no effect */
		/* Transmitter CTS has no effect */
		| MCF5307_UART_UMR2_STOP_BITS(7)	/* 1 stop bit	*/
		) ;
	imm->uart1.USR1_UCSR1 = ( 0
		| MCF5307_UART_UCSR_RCS(0xd)	/* Set receiver baud by timer	*/
		| MCF5307_UART_UCSR_TCS(0xd)	/* Set transmitter baud by timer*/
		) ;
	imm->uart1.UIPCR1_UACR1 = ( 0
		| MCF5307_UART_UACR_CTMS_TIMER	/* Set baud by timers	*/
		) ;
	imm->uart1.UISR1_UIMR1 = 0;		/* Disable all interrupts	*/


	imm->uart1.UBG11 = 0;
	imm->uart1.UBG21 = 0x49;		/* Set baud to 19200	*/

	/************************************************************************/
	/*  UART 2								*/
	/************************************************************************/

	imm->uart2.UCR2 = ( 0		/* Disable UART 2 */
		| MCF5307_UART_UCR_TX_DISABLED
		| MCF5307_UART_UCR_RX_DISABLED
		) ;
}

void
mcf5307_cs_init (MCF5307_IMM *imm)
{
	 unsigned short int Temp;
        /************************************************************************/
        /*                                                                      */
        /*  This routine initializes ChipSelects to setup peripherals.          */
        /*                                                                      */
        /************************************************************************/
        /************************************************************************/
        /*  ChipSelect 0 - Boot FLASH 28F800                                    */
        /*                                                                      */
        /*  ChipSelect 0 is the global chip select coming out of system reset.  */
        /*  CS0 is asserted for every access until CSMR0 is written.            */
        /*  Therefore, the entire ChipSelect must be properly set prior to      */
        /*  asserting CSCR0_V.                                                  */
        /************************************************************************/
        imm->cs.CSAR0 = 0xff00;
        imm->cs.CSCR0 = ( 0
                | MCF5307_CS_CSCR_WS(4)
                | MCF5307_CS_CSCR_AA    /* TA_ generated internally */
                | MCF5307_CS_CSCR_PS_16 ) ;
        imm->cs.CSMR0 = ( 0
                | MCF5307_CS_CSMR_MASK_2M
                | MCF5307_CS_CSMR_V ) ;
 
	
        /************************************************************************/
        /*  ChipSelect 1 - Flash-Memory                                         */
        /************************************************************************/
	imm->cs.CSAR1 = 0xff20;     //
        imm->cs.CSCR1 = ( 0
                | MCF5307_CS_CSCR_WS(4)
                | MCF5307_CS_CSCR_AA    /* TA_ generated internally */
                | MCF5307_CS_CSCR_PS_16 ) ;
        imm->cs.CSMR1 = ( 0
                | MCF5307_CS_CSMR_MASK_2M   //kang  
                | MCF5307_CS_CSMR_V ) ;
        /************************************************************************/
        /*  ChipSelect 2 - I/O                                                  */
        /************************************************************************/
      
	imm->cs.CSAR2 = 0x2200;	
        imm->cs.CSCR2 = ( 0
			| MCF5307_CS_CSCR_WS(15)
                	| MCF5307_CS_CSCR_AA    /* TA_ generated internally */       		
		        | MCF5307_CS_CSCR_PS_16 ) ;
        imm->cs.CSMR2 = ( 0
                	| MCF5307_CS_CSMR_MASK_16M
                	| MCF5307_CS_CSMR_V ) ;
         /************************************************************************/
        /*  ChipSelect 3 - VRAM-Display                                          */
        /************************************************************************/
        
#ifdef OldBoard        
	imm->cs.CSAR3 = 0x3040;
#else
	imm->cs.CSAR3 = 0x3300;
#endif	        
	
        imm->cs.CSCR3 = ( 0
	  	| MCF5307_CS_CSCR_WS(15)
                | MCF5307_CS_CSCR_AA
                | MCF5307_CS_CSCR_BEM	    
                | MCF5307_CS_CSCR_PS_16 ) ;
        imm->cs.CSMR3 = ( 0
                | MCF5307_CS_CSMR_MASK_64K
                | MCF5307_CS_CSMR_V ) ;
         
        /************************************************************************/
        /*  ChipSelect 4 - Hard-Disk                                            */
        /************************************************************************/
        imm->cs.CSAR4 = 0x3080;
	imm->cs.CSCR4 = ( 0
		| MCF5307_CS_CSCR_WS(5)
                | MCF5307_CS_CSCR_AA    /* TA_ generated internally */
	        | MCF5307_CS_CSCR_PS_16 ) ;
	imm->cs.CSMR4 = ( 0
		| MCF5307_CS_CSMR_MASK_64K		
                | MCF5307_CS_CSMR_V ) ;
                /************************************************************************/
        /*  ChipSelect 5 - Super I/O                                            */
        /************************************************************************/
        imm->cs.CSAR5 = 0x30A0;
          Temp=(0
        	| MCF5307_CS_CSCR_WS(8)
                | MCF5307_CS_CSCR_AA    
	        | MCF5307_CS_CSCR_PS_8);
        
        
	imm->cs.CSCR5 = Temp;
	
	Temp=(0 | MCF5307_CS_CSMR_MASK_64K
                | MCF5307_CS_CSMR_V ) ;
	
	imm->cs.CSMR5 = Temp;
	
                /************************************************************************/
        /*  ChipSelect 6 - A/D FIFO                                             */
        /************************************************************************/
        Temp=(0| MCF5307_CS_CSCR_WS(1)  | MCF5307_CS_CSCR_AA | MCF5307_CS_CSCR_PS_16);
        
        imm->cs.CSAR6 = 0x30C0;
	imm->cs.CSCR6 = ( Temp) ;
        imm->cs.CSMR6 = ( 0
		| MCF5307_CS_CSMR_MASK_64K
                | MCF5307_CS_CSMR_V ) ;
        
        /************************************************************************/
        /*  ChipSelect 7 - Recorder                                             */
        /************************************************************************/
        imm->cs.CSAR7 = 0x30E0;
	imm->cs.CSCR7 = ( 0
		| MCF5307_CS_CSCR_WS(3)
                | MCF5307_CS_CSCR_AA    /* TA_ generated internally */
                | MCF5307_CS_CSCR_PS_8 ) ;
        imm->cs.CSMR7 = ( 0
		| MCF5307_CS_CSMR_MASK_64K
                | MCF5307_CS_CSMR_V ) ;
	/************************************************************************/
        /*  ChipSelect 1,3,4,5,6 and 7 - Invalid                                    */
        /************************************************************************/
        //imm->cs.CSMR0 = 0;
        //imm->cs.CSMR1 = 0;
        //imm->cs.CSMR2 = 0; 
        //imm->cs.CSMR3 = 0;
        //imm->cs.CSMR4 = 0;
        //imm->cs.CSMR5 = 0;
        //imm->cs.CSMR6 = 0;
        //imm->cs.CSMR7 = 0;         
}