mcf5307.h

一个外国牛人做的ucos2向mcf5307的移植

 /*******************************************************************************/
 /*										*/
 /*  The last few registers can only be accessed as a read or write register.	*/
 /*										*/
 /*******************************************************************************/

#define MCF5307_UART_UIP_CTS			(0x01) /* Current State of CTS Input	*/

#define MCF5307_UART_UOP_RTS			(0x01) /* Sets All Bits on OP Bit Set	*/
#define MCF5307_UART_UOP0_RTS			(0x01) /* Clears All Bits on OP Bit Rst	*/


/************************************************************************/
/*									*/
/*  Parallel Port Registers						*/
/*									*/
/************************************************************************/

typedef volatile struct
{
	NATURAL32	reserved0[0x91];
	NATURAL16	PADDR;		/* Port A Data Direction Register	*/
	NATURAL16	reserved1;
	NATURAL16	PADAT;		/* Port A Data Register			*/
	NATURAL16	reserved2;
} MCF5307_PPORT;

#define MCF5307_PPORT_PADDR_15	(0x8000)	/* Bit 15 General I/O Output	*/
#define MCF5307_PPORT_PADDR_14	(0x4000)	/* Bit 14 General I/O Output	*/
#define MCF5307_PPORT_PADDR_13	(0x2000)	/* Bit 13 General I/O Output	*/
#define MCF5307_PPORT_PADDR_12	(0x1000)	/* Bit 12 General I/O Output	*/
#define MCF5307_PPORT_PADDR_11	(0x0800)	/* Bit 11 General I/O Output	*/
#define MCF5307_PPORT_PADDR_10	(0x0400)	/* Bit 10 General I/O Output	*/
#define MCF5307_PPORT_PADDR_9	(0x0200)	/* Bit  9 General I/O Output	*/
#define MCF5307_PPORT_PADDR_8	(0x0100)	/* Bit  8 General I/O Output	*/
#define MCF5307_PPORT_PADDR_7	(0x0080)	/* Bit  7 General I/O Output	*/
#define MCF5307_PPORT_PADDR_6	(0x0040)	/* Bit  6 General I/O Output	*/
#define MCF5307_PPORT_PADDR_5	(0x0020)	/* Bit  5 General I/O Output	*/
#define MCF5307_PPORT_PADDR_4	(0x0010)	/* Bit  4 General I/O Output	*/
#define MCF5307_PPORT_PADDR_3	(0x0008)	/* Bit  3 General I/O Output	*/
#define MCF5307_PPORT_PADDR_2	(0x0004)	/* Bit  2 General I/O Output	*/
#define MCF5307_PPORT_PADDR_1	(0x0002)	/* Bit  1 General I/O Output	*/
#define MCF5307_PPORT_PADDR_0	(0x0001)	/* Bit  0 General I/O Output	*/

#define MCF5307_PPORT_PADAT_15	(0x8000)	/* Bit 15 Current Status	*/
#define MCF5307_PPORT_PADAT_14	(0x4000)	/* Bit 14 Current Status	*/
#define MCF5307_PPORT_PADAT_13	(0x2000)	/* Bit 13 Current Status	*/
#define MCF5307_PPORT_PADAT_12	(0x1000)	/* Bit 12 Current Status	*/
#define MCF5307_PPORT_PADAT_11	(0x0800)	/* Bit 11 Current Status	*/
#define MCF5307_PPORT_PADAT_10	(0x0400)	/* Bit 10 Current Status	*/
#define MCF5307_PPORT_PADAT_9	(0x0200)	/* Bit  9 Current Status	*/
#define MCF5307_PPORT_PADAT_8	(0x0100)	/* Bit  8 Current Status	*/
#define MCF5307_PPORT_PADAT_7	(0x0080)	/* Bit  7 Current Status	*/
#define MCF5307_PPORT_PADAT_6	(0x0040)	/* Bit  6 Current Status	*/
#define MCF5307_PPORT_PADAT_5	(0x0020)	/* Bit  5 Current Status	*/
#define MCF5307_PPORT_PADAT_4	(0x0010)	/* Bit  4 Current Status	*/
#define MCF5307_PPORT_PADAT_3	(0x0008)	/* Bit  3 Current Status	*/
#define MCF5307_PPORT_PADAT_2	(0x0004)	/* Bit  2 Current Status	*/
#define MCF5307_PPORT_PADAT_1	(0x0002)	/* Bit  1 Current Status	*/
#define MCF5307_PPORT_PADAT_0	(0x0001)	/* Bit  0 Current Status	*/


/************************************************************************/
/*									*/
/*  M-BUS Registers							*/
/*									*/
/************************************************************************/

typedef volatile struct
{
	NATURAL32	reserved0[0xa0];
	NATURAL8	MADR;		/* M-Bus Address Register		*/
	NATURAL8	reserved1;
	NATURAL16	reserved2;
	NATURAL8	MFDR;		/* M-Bus Frequency Divider Register	*/
	NATURAL8	reserved3;
	NATURAL16	reserved4;
	NATURAL8	MBCR;		/* M-Bus Control Register		*/
	NATURAL8	reserved5;
	NATURAL16	reserved6;
	NATURAL8	MBSR;		/* M-Bus Status Register		*/
	NATURAL8	reserved7;
	NATURAL16	reserved8;
	NATURAL8	MBDR;		/* M-Bus Data I/O Register		*/
} MCF5307_MBUS;

#define MCF5307_MBUS_MADR_ADDR(a)	(((a)&0xFE)<<0x01) /* Slave Address	*/

#define MCF5307_MBUS_MFDR_MBC(a)	((a)&0x3F)	/* M-Bus Clock Rate	*/

#define MCF5307_MBUS_MBCR_MEN		(0x80)	/* M-Bus Enable			*/
#define MCF5307_MBUS_MBCR_MIEN		(0x40)	/* M-Bus Interrupt Enable	*/
#define MCF5307_MBUS_MBCR_MSTA		(0x20)	/* Master/Slave Mode Select Bit	*/
#define MCF5307_MBUS_MBCR_MTX		(0x10)	/* Transmit/Rcv Mode Select Bit	*/
#define MCF5307_MBUS_MBCR_TXAK		(0x08)	/* Transmit Acknowledge Enable	*/
#define MCF5307_MBUS_MBCR_RSTA		(0x04)	/* Repeat Start			*/

#define MCF5307_MBUS_MBSR_MCF		(0x80)	/* Data Transfer Complete	*/
#define MCF5307_MBUS_MBSR_MAAS		(0x40)	/* Addressed as a Slave		*/
#define MCF5307_MBUS_MBSR_MBB		(0x20)	/* Bus Busy			*/
#define MCF5307_MBUS_MBSR_MAL		(0x10)	/* Arbitration Lost		*/
#define MCF5307_MBUS_MBSR_SRW		(0x04)	/* Slave Transmit		*/
#define MCF5307_MBUS_MBSR_MIF		(0x02)	/* M-Bus Interrupt		*/
#define MCF5307_MBUS_MBSR_RXAK		(0x01)	/* No Acknowledge Received	*/


/************************************************************************/
/*									*/
/*  DMA Registers							*/
/*									*/
/************************************************************************/

typedef volatile struct
{
	NATURAL32	reserved0[0xc0];
	NATURAL32	SAR0;		/* DMA 0 Source Address Register	*/
	NATURAL32	DAR0;		/* DMA 0 Destination Address Register	*/
	NATURAL16	DCR0;		/* DMA 0 Control Register		*/
	NATURAL16	reserved1;
	NATURAL16	BCR0;		/* DMA 0 Byte Count Register		*/
	NATURAL16	reserved2;
	NATURAL8	DSR0;		/* DMA 0 Status Register		*/
	NATURAL8	reserved3;
	NATURAL16	reserved4;
	NATURAL8	DIVR0;		/* DMA 0 Interrupt Vector Register	*/
	NATURAL8	reserved5;
	NATURAL16	reserved6;
	NATURAL32	reserved7[0xa];
	NATURAL32	SAR1;		/* DMA 1 Source Address Register	*/
	NATURAL32	DAR1;		/* DMA 1 Destination Address Register	*/
	NATURAL16	DCR1;		/* DMA 1 Control Register		*/
	NATURAL16	reserved8;
	NATURAL16	BCR1;		/* DMA 1 Byte Count Register		*/
	NATURAL16	reserved9;
	NATURAL8	DSR1;		/* DMA 1 Status Register		*/
	NATURAL8	reserved10;
	NATURAL16	reserved11;
	NATURAL8	DIVR1;		/* DMA 1 Interrupt Vector Register	*/
	NATURAL8	reserved12;
	NATURAL16	reserved13;
	NATURAL32	reserved14[0xa];
	NATURAL32	SAR2;		/* DMA 2 Source Address Register	*/
	NATURAL32	DAR2;		/* DMA 2 Destination Address Register	*/
	NATURAL16	DCR2;		/* DMA 2 Control Register		*/
	NATURAL16	reserved15;
	NATURAL16	BCR2;		/* DMA 2 Byte Count Register		*/
	NATURAL16	reserved16;
	NATURAL8	DSR2;		/* DMA 2 Status Register		*/
	NATURAL8	reserved17;
	NATURAL16	reserved18;
	NATURAL8	DIVR2;		/* DMA 2 Interrupt Vector Register	*/
	NATURAL8	reserved19;
	NATURAL16	reserved20;
	NATURAL32	reserved21[0xa];
	NATURAL32	SAR3;		/* DMA 3 Source Address Register	*/
	NATURAL32	DAR3;		/* DMA 3 Destination Address Register	*/
	NATURAL16	DCR3;		/* DMA 3 Control Register		*/
	NATURAL16	reserved22;
	NATURAL16	BCR3;		/* DMA 3 Byte Count Register		*/
	NATURAL16	reserved23;
	NATURAL8	DSR3;		/* DMA 3 Status Register		*/
	NATURAL8	reserved24;
	NATURAL16	reserved25;
	NATURAL8	DIVR3;		/* DMA 3 Interrupt Vector Register	*/
} MCF5307_DMA;

#define MCF5307_DMA_DCR_INT		(0x8000) /* Interrupt on Completion	*/
#define MCF5307_DMA_DCR_EEXT		(0x4000) /* Enable External Request	*/
#define MCF5307_DMA_DCR_CS		(0x2000) /* Cycle Steal			*/
#define MCF5307_DMA_DCR_AA		(0x1000) /* Auto Align			*/
#define MCF5307_DMA_DCR_BWC_DMA		(0x0000) /* Bandwidth: DMA Priority	*/
#define MCF5307_DMA_DCR_BWC_512		(0x0200) /* Bandwidth:   512 Bytes	*/
#define MCF5307_DMA_DCR_BWC_1024	(0x0400) /* Bandwidth:  1024 Bytes	*/
#define MCF5307_DMA_DCR_BWC_2048	(0x0600) /* Bandwidth:  2048 Bytes	*/
#define MCF5307_DMA_DCR_BWC_4096	(0x0800) /* Bandwidth:  4096 Bytes	*/
#define MCF5307_DMA_DCR_BWC_8192	(0x0a00) /* Bandwidth:  8192 Bytes	*/
#define MCF5307_DMA_DCR_BWC_16384	(0x0c00) /* Bandwidth: 16384 Bytes	*/
#define MCF5307_DMA_DCR_BWC_32768	(0x0e00) /* Bandwidth: 32768 Bytes	*/
#define MCF5307_DMA_DCR_SAA		(0x0100) /* Single Address Access	*/
#define MCF5307_DMA_DCR_SRW		(0x0080) /* Forces MRW Signal High	*/
#define	MCF5307_DMA_DCR_SINC		(0x0040) /* Source Increment		*/
#define MCF5307_DMA_DCR_SSIZE_LONG	(0x0000) /* Source Size:  Longword	*/
#define MCF5307_DMA_DCR_SSIZE_BYTE	(0x0010) /* Source Size:  Byte		*/
#define MCF5307_DMA_DCR_SSIZE_WORD	(0x0020) /* Source Size:  Word		*/
#define MCF5307_DMA_DCR_SSIZE_LINE	(0x0030) /* Source Size:  Line		*/
#define MCF5307_DMA_DCR_DINC		(0x0008) /* Destination Increment	*/
#define MCF5307_DMA_DCR_DSIZE_LONG	(0x0000) /* Destination Size:  Longword	*/
#define MCF5307_DMA_DCR_DSIZE_BYTE	(0x0002) /* Destination Size:  Byte	*/
#define MCF5307_DMA_DCR_DSIZE_WORD	(0x0004) /* Destination Size:  Word	*/
#define MCF5307_DMA_DCR_START		(0x0001) /* Start Transfer		*/

#define MCF5307_DMA_DSR_CE		(0x40)	/* Configuration Error		*/
#define MCF5307_DMA_DSR_BES		(0x20)	/* Bus Error on Source		*/
#define MCF5307_DMA_DSR_BED		(0x10)	/* Bus Error on Destination	*/
#define MCF5307_DMA_DSR_REQ		(0x04)	/* Request			*/
#define MCF5307_DMA_DSR_BSY		(0x02)	/* Busy				*/
#define MCF5307_DMA_DSR_DONE		(0x01)	/* Transaction Done		*/


/****************************************************************************************/
/*											*/
/*  Here we put the modules together.  An example access for the UART mode		*/
/*  register would be: (assuming we have a pointer to the IMM):				*/
/*											*/
/*   imm->uart1.UMR									*/
/*											*/
/****************************************************************************************/

typedef volatile union
{
	MCF5307_SIM	sim;
	MCF5307_CS	cs;
	MCF5307_DRAMC	dramc;
	MCF5307_TIMER	timer;
	MCF5307_UART1	uart1;
	MCF5307_UART2	uart2;
	MCF5307_PPORT	parallel_port;
	MCF5307_MBUS	mbus;
	MCF5307_DMA	dma;
} MCF5307_IMM;


/************************************************************************/
/*									*/
/*  Function prototypes							*/
/*									*/
/************************************************************************/

void
ird (int, char **);

void
irm (int, char **);

void
mcf5307_write_cacr (NATURAL32);

void
mcf5307_write_acr0 (NATURAL32);

void
mcf5307_write_acr1 (NATURAL32);

void
mcf5307_write_vbr (NATURAL32);

void
mcf5307_write_srambar (NATURAL32);

void
mcf5307_write_mbar (NATURAL32);


#endif	/* MCF5307_H */