📄 mcf5307.h
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#define MCF5307_SIM_PLLCR_ENBSTOP (0x80) /* Enable CPU STOP Instruction */
#define MCF5307_SIM_PLLCR_PLLIPL(a) (((a)&0x07)<<4) /* PLL Wake-up IPL */
#define MCF5307_SIM_MPARK_PARK(a) (((a)&0x03)<<6) /* Default Bus Master */
#define MCF5307_SIM_MPARK_E2MCTRL (0x20) /* EBus to MBus Arbitration */
#define MCF5307_SIM_MPARK_EARBCTRL (0x10) /* SBus to EBus Arbitration */
#define MCF5307_SIM_MPARK_SHOWDATA (0x08) /* Show SBus on EBus */
#define MCF5307_SIM_IPR_DMA3 (0x00020000) /* Interrupt Pending DMA3 */
#define MCF5307_SIM_IPR_DMA2 (0x00010000) /* Interrupt Pending DMA2 */
#define MCF5307_SIM_IPR_DMA1 (0x00008000) /* Interrupt Pending DMA1 */
#define MCF5307_SIM_IPR_DMA0 (0x00004000) /* Interrupt Pending DMA0 */
#define MCF5307_SIM_IPR_UART2 (0x00002000) /* Interrupt Pending UART2 */
#define MCF5307_SIM_IPR_UART1 (0x00001000) /* Interrupt Pending UART1 */
#define MCF5307_SIM_IPR_MBUS (0x00000800) /* Interrupt Pending MBUS */
#define MCF5307_SIM_IPR_TIMER2 (0x00000400) /* Interrupt Pending TIMER2 */
#define MCF5307_SIM_IPR_TIMER1 (0x00000200) /* Interrupt Pending TIMER1 */
#define MCF5307_SIM_IPR_SWT (0x00000100) /* Interrupt Pending SWT */
#define MCF5307_SIM_IPR_EINT7 (0x00000080) /* Interrupt Pending EINT7 */
#define MCF5307_SIM_IPR_EINT6 (0x00000040) /* Interrupt Pending EINT7 */
#define MCF5307_SIM_IPR_EINT5 (0x00000020) /* Interrupt Pending EINT7 */
#define MCF5307_SIM_IPR_EINT4 (0x00000010) /* Interrupt Pending EINT7 */
#define MCF5307_SIM_IPR_EINT3 (0x00000008) /* Interrupt Pending EINT7 */
#define MCF5307_SIM_IPR_EINT2 (0x00000004) /* Interrupt Pending EINT7 */
#define MCF5307_SIM_IPR_EINT1 (0x00000002) /* Interrupt Pending EINT7 */
#define MCF5307_SIM_IMR_DMA3 (0x00020000) /* Mask DMA3 */
#define MCF5307_SIM_IMR_DMA2 (0x00010000) /* Mask DMA2 */
#define MCF5307_SIM_IMR_DMA1 (0x00008000) /* Mask DMA1 */
#define MCF5307_SIM_IMR_DMA0 (0x00004000) /* Mask DMA0 */
#define MCF5307_SIM_IMR_UART2 (0x00002000) /* Mask UART2 */
#define MCF5307_SIM_IMR_UART1 (0x00001000) /* Mask UART1 */
#define MCF5307_SIM_IMR_MBUS (0x00000800) /* Mask MBUS */
#define MCF5307_SIM_IMR_TIMER2 (0x00000400) /* Mask TIMER2 */
#define MCF5307_SIM_IMR_TIMER1 (0x00000200) /* Mask TIMER1 */
#define MCF5307_SIM_IMR_SWT (0x00000100) /* Mask SWT */
#define MCF5307_SIM_IMR_EINT7 (0x00000080) /* Mask EINT7 */
#define MCF5307_SIM_IMR_EINT6 (0x00000040) /* Mask EINT6 */
#define MCF5307_SIM_IMR_EINT5 (0x00000020) /* Mask EINT5 */
#define MCF5307_SIM_IMR_EINT4 (0x00000010) /* Mask EINT4 */
#define MCF5307_SIM_IMR_EINT3 (0x00000008) /* Mask EINT3 */
#define MCF5307_SIM_IMR_EINT2 (0x00000004) /* Mask EINT2 */
#define MCF5307_SIM_IMR_EINT1 (0x00000002) /* Mask EINT1 */
#define MCF5307_SIM_AVCR_AVEC7 (0x80) /* Auto Vector Ext Interrupt 7 */
#define MCF5307_SIM_AVCR_AVEC6 (0x40) /* Auto Vector Ext Interrupt 6 */
#define MCF5307_SIM_AVCR_AVEC5 (0x20) /* Auto Vector Ext Interrupt 5 */
#define MCF5307_SIM_AVCR_AVEC4 (0x10) /* Auto Vector Ext Interrupt 4 */
#define MCF5307_SIM_AVCR_AVEC3 (0x08) /* Auto Vector Ext Interrupt 3 */
#define MCF5307_SIM_AVCR_AVEC2 (0x04) /* Auto Vector Ext Interrupt 2 */
#define MCF5307_SIM_AVCR_AVEC1 (0x02) /* Auto Vector Ext Interrupt 1 */
#define MCF5307_SIM_AVCR_BLK (0x01) /* Block Address Strobe */
#define MCF5307_SIM_ICR_AVEC (0x80) /* Autovector Enable */
#define MCF5307_SIM_ICR_IL(a) (((a)&0x07)<<2) /* Interrupt Level */
#define MCF5307_SIM_ICR_IP_EXT (0x02) /* High Priority External */
#define MCF5307_SIM_ICR_IP_INT (0x01) /* High Priority Internal */
/************************************************************************/
/* */
/* Chip Select Registers */
/* */
/************************************************************************/
typedef volatile struct
{
NATURAL32 reserved1[0x20];
NATURAL16 CSAR0; /* Chip-Select Address Register - Bank 0 */
NATURAL16 reserved2;
NATURAL32 CSMR0; /* Chip-Select Mask Register - Bank 0 */
NATURAL16 reserved3;
NATURAL16 CSCR0; /* Chip-Select Control Register - Bank 0 */
NATURAL16 CSAR1; /* Chip-Select Address Register - Bank 1 */
NATURAL16 reserved4;
NATURAL32 CSMR1; /* Chip-Select Mask Register - Bank 1 */
NATURAL16 reserved5;
NATURAL16 CSCR1; /* Chip-Select Control Register - Bank 1 */
NATURAL8 CSBAR; /* Chip-Select Address Register - Banks 2-7 */
NATURAL8 reserved6;
NATURAL16 reserved7;
NATURAL32 CSMR2; /* Chip-Select Mask Register - Bank 2 */
NATURAL16 reserved8;
NATURAL16 CSCR2; /* Chip-Select Control Register - Bank 2 */
NATURAL32 reserved9;
NATURAL32 CSMR3; /* Chip-Select Mask Register - Bank 3 */
NATURAL16 reserved10;
NATURAL16 CSCR3; /* Chip-Select Control Register - Bank 3 */
NATURAL32 reserved11;
NATURAL32 CSMR4; /* Chip-Select Mask Register - Bank 4 */
NATURAL16 reserved12;
NATURAL16 CSCR4; /* Chip-Select Control Register - Bank 4 */
NATURAL32 reserved13;
NATURAL32 CSMR5; /* Chip-Select Mask Register - Bank 5 */
NATURAL16 reserved14;
NATURAL16 CSCR5; /* Chip-Select Control Register - Bank 5 */
NATURAL32 reserved15;
NATURAL32 CSMR6; /* Chip-Select Mask Register - Bank 6 */
NATURAL16 reserved16;
NATURAL16 CSCR6; /* Chip-Select Control Register - Bank 6 */
NATURAL32 reserved17;
NATURAL32 CSMR7; /* Chip-Select Mask Register - Bank 7 */
NATURAL16 reserved18;
NATURAL16 CSCR7; /* Chip-Select Control Register - Bank 7 */
} MCF5307_CS;
/***********************************************************************/
/* */
/* These definitions only exists in the CSMR for Banks 0 and 1. */
/* */
/***********************************************************************/
#define MCF5307_CS_CSMR_MASK_4G (0xFFFF0000) /* Set Bank to 4G */
#define MCF5307_CS_CSMR_MASK_2G (0x7FFF0000) /* Set Bank to 2G */
#define MCF5307_CS_CSMR_MASK_1G (0x3FFF0000) /* Set Bank to 1G */
#define MCF5307_CS_CSMR_MASK_1024M (0x3FFF0000) /* Set Bank to 1024M */
#define MCF5307_CS_CSMR_MASK_512M (0x1FFF0000) /* Set Bank to 512M */
#define MCF5307_CS_CSMR_MASK_256M (0x0FFF0000) /* Set Bank to 256M */
#define MCF5307_CS_CSMR_MASK_128M (0x07FF0000) /* Set Bank to 128M */
#define MCF5307_CS_CSMR_MASK_64M (0x03FF0000) /* Set Bank to 64M */
#define MCF5307_CS_CSMR_MASK_32M (0x01FF0000) /* Set Bank to 32M */
#define MCF5307_CS_CSMR_MASK_16M (0x00FF0000) /* Set Bank to 16M */
#define MCF5307_CS_CSMR_MASK_8M (0x007F0000) /* Set Bank to 8M */
#define MCF5307_CS_CSMR_MASK_4M (0x003F0000) /* Set Bank to 4M */
#define MCF5307_CS_CSMR_MASK_2M (0x001F0000) /* Set Bank to 2M */
#define MCF5307_CS_CSMR_MASK_1M (0x000F0000) /* Set Bank to 1M */
#define MCF5307_CS_CSMR_MASK_1024K (0x000F0000) /* Set Bank to 1024K */
#define MCF5307_CS_CSMR_MASK_512K (0x00070000) /* Set Bank to 512K */
#define MCF5307_CS_CSMR_MASK_256K (0x00030000) /* Set Bank to 256K */
#define MCF5307_CS_CSMR_MASK_128K (0x00010000) /* Set Bank to 128K */
#define MCF5307_CS_CSMR_MASK_64K (0x00000000) /* Set Bank to 64K */
#define MCF5307_CS_CSMR_CPU (0x00000020) /* CPU and IACK Cycle Mask */
/***********************************************************************/
/* */
/* The following definitions exist for all Banks 0-7 */
/* */
/***********************************************************************/
#define MCF5307_CS_CSAR(a) (((a)&0xFFFF0000)>>16) /* Base Address */
#define MCF5307_CS_CSBAR(a) (((a)&0xFF000000)>>24) /* Base for CS2-7 */
#define MCF5307_CS_CSMR_WP (0x00000100) /* Write Protect */
#define MCF5307_CS_CSMR_AM (0x00000040) /* Alternate Master Mask */
#define MCF5307_CS_CSMR_SC (0x00000010) /* Supervisor Code Mask */
#define MCF5307_CS_CSMR_SD (0x00000008) /* Supervisor Data Mask */
#define MCF5307_CS_CSMR_UC (0x00000004) /* User Code Mask */
#define MCF5307_CS_CSMR_UD (0x00000002) /* User Data Mask */
#define MCF5307_CS_CSMR_V (0x00000001) /* Valid Register */
#define MCF5307_CS_CSCR_WS(a) (((a)&0x0F)<<10) /* Wait States */
#define MCF5307_CS_CSCR_AA (0x0100) /* Auto Acknowledge Enable */
#define MCF5307_CS_CSCR_PS_8 (0x0040) /* Port Size: 8-bit */
#define MCF5307_CS_CSCR_PS_16 (0x0080) /* Port Size: 16-bit */
#define MCF5307_CS_CSCR_PS_32 (0x0000) /* Port Size: 32-bit */
#define MCF5307_CS_CSCR_BEM (0x0020) /* Byte Module Enable */
#define MCF5307_CS_CSCR_BSTR (0x0010) /* Burst Read Enable */
#define MCF5307_CS_CSCR_BSTW (0x0008) /* Burst Write Enable */
/************************************************************************/
/* */
/* DRAM Registers */
/* */
/************************************************************************/
typedef volatile struct
{
NATURAL32 reserved1[0x40];
NATURAL16 DCR; /* DRAM Control Register */
NATURAL16 reserved2;
NATURAL32 reserved3;
NATURAL32 DACR0; /* DRAM Address and Control Register 0 */
NATURAL32 DCMR0; /* DRAM Controller Mask Register 0 */
NATURAL32 DACR1; /* DRAM Address and Control Register 1 */
NATURAL32 DCMR1; /* DRAM Controller Mask Register 1 */
} MCF5307_DRAMC;
/***********************************************************************/
/* */
/* Controls used by both Synchronous and Asynchronous DRAM */
/* */
/***********************************************************************/
#define MCF5307_DRAMC_DCR_SO (0x8000) /* Synchronous Operation */
#define MCF5307_DRAMC_DCR_NAM (0x2000) /* No Address Multiplexing */
#define MCF5307_DRAMC_DCR_RC(a) ((a)&0x01FF) /* Refresh Count */
#define MCF5307_DRAMC_DACR_BASE(a) ((a)&0xFFFC0000) /* Base Address */
#define MCF5307_DRAMC_DACR_RE (0x00008000) /* Refresh Enable */
#define MCF5307_DRAMC_DACR_PS_32 (0x00000000) /* Port Size: 32-bit */
#define MCF5307_DRAMC_DACR_PS_8 (0x00000010) /* Port Size: 8-bit */
#define MCF5307_DRAMC_DACR_PS_16 (0x00000020) /* Port Size: 16-bit */
#define MCF5307_DRAMC_DCMR_MASK_4G (0xFFFC0000) /* DRAM Size of 4G */
#define MCF5307_DRAMC_DCMR_MASK_2G (0x7FFC0000) /* DRAM Size of 2G */
#define MCF5307_DRAMC_DCMR_MASK_1G (0x3FFC0000) /* DRAM Size of 1G */
#define MCF5307_DRAMC_DCMR_MASK_1024M (0x3FFC0000) /* DRAM Size of 1024M */
#define MCF5307_DRAMC_DCMR_MASK_512M (0x1FFC0000) /* DRAM Size of 512M */
#define MCF5307_DRAMC_DCMR_MASK_256M (0x0FFC0000) /* DRAM Size of 256M */
#define MCF5307_DRAMC_DCMR_MASK_128M (0x07FC0000) /* DRAM Size of 128M */
#define MCF5307_DRAMC_DCMR_MASK_64M (0x03FC0000) /* DRAM Size of 64M */
#define MCF5307_DRAMC_DCMR_MASK_32M (0x01FC0000) /* DRAM Size of 32M */
#define MCF5307_DRAMC_DCMR_MASK_16M (0x00FC0000) /* DRAM Size of 16M */
#define MCF5307_DRAMC_DCMR_MASK_8M (0x007C0000) /* DRAM Size of 8M */
#define MCF5307_DRAMC_DCMR_MASK_4M (0x003C0000) /* DRAM Size of 4M */
#define MCF5307_DRAMC_DCMR_MASK_2M (0x001C0000) /* DRAM Size of 2M */
#define MCF5307_DRAMC_DCMR_MASK_1M (0x000C0000) /* DRAM Size of 1M */
#define MCF5307_DRAMC_DCMR_MASK_1024K (0x00040000) /* DRAM Size of 1024K */
#define MCF5307_DRAMC_DCMR_MASK_256K (0x00000000) /* DRAM Size of 512K */
#define MCF5307_DRAMC_DCMR_WP (0x00000100) /* Write Protect */
#define MCF5307_DRAMC_DCMR_CPU (0x00000040) /* CPU Space Ignored */
#define MCF5307_DRAMC_DCMR_AM (0x00000020) /* Alternate Master Ignored */
#define MCF5307_DRAMC_DCMR_SC (0x00000010) /* Supervisor Code Ignored */
#define MCF5307_DRAMC_DCMR_SD (0x00000008) /* Supervisor Data Ignored */
#define MCF5307_DRAMC_DCMR_UC (0x00000004) /* User Code Ignored */
#define MCF5307_DRAMC_DCMR_UD (0x00000002) /* User Data Ignored */
#define MCF5307_DRAMC_DCMR_V (0x00000001) /* Valid Register */
/***********************************************************************/
/* */
/* Controls used only by Asynchronous DRAM */
/* */
/***********************************************************************/
#define MCF5307_DRAMC_DCR_RRA_2 (0x0000) /* Refresh RAS Asserted 2 Clocks */
#define MCF5307_DRAMC_DCR_RRA_3 (0x0800) /* Refresh RAS Asserted 3 Clocks */
#define MCF5307_DRAMC_DCR_RRA_4 (0x1000) /* Refresh RAS Asserted 4 Clocks */
#define MCF5307_DRAMC_DCR_RRA_5 (0x1800) /* Refresh RAS Asserted 5 Clocks */
#define MCF5307_DRAMC_DCR_RRP_1 (0x0000) /* Refresh RAS Precharged 3 Clks */
#define MCF5307_DRAMC_DCR_RRP_2 (0x0200) /* Refresh RAS Precharged 3 Clks */
#define MCF5307_DRAMC_DCR_RRP_3 (0x0400) /* Refresh RAS Precharged 3 Clks */
#define MCF5307_DRAMC_DCR_RRP_4 (0x0600) /* Refresh RAS Precharged 3 Clks */
#define MCF5307_DRAMC_DACR_CAS_1 (0x00000000) /* CAS Active 1 Clock */
#define MCF5307_DRAMC_DACR_CAS_2 (0x00001000) /* CAS Active 2 Clocks */
#define MCF5307_DRAMC_DACR_CAS_3 (0x00002000) /* CAS Active 3 Clocks */
#define MCF5307_DRAMC_DACR_CAS_4 (0x00003000) /* CAS Active 4 Clocks */
#define MCF5307_DRAMC_DACR_RP_1 (0x00000000) /* RAS Precharge 1 Clock */
#define MCF5307_DRAMC_DACR_RP_2 (0x00000400) /* RAS Precharge 2 Clocks */
#define MCF5307_DRAMC_DACR_RP_3 (0x00000800) /* RAS Precharge 3 Clocks */
#define MCF5307_DRAMC_DACR_RP_4 (0x00000C00) /* RAS Precharge 4 Clocks */
#define MCF5307_DRAMC_DACR_RNCN (0x00000200) /* RAS Negate to CAS Negate */
#define MCF5307_DRAMC_DACR_RCD_1 (0x00000000) /* 1 Clock Between RAS and CAS */
#define MCF5307_DRAMC_DACR_RCD_2 (0x00000100) /* 2 Clocks Between RAS and CAS */
#define MCF5307_DRAMC_DACR_EDO (0x00000040) /* Extended Data Out */
#define MCF5307_DRAMC_DACR_PM_OFF (0x00000000) /* No Page Mode */
#define MCF5307_DRAMC_DACR_PM_BURST (0x00000004) /* Page Mode on Burst Only */
#define MCF5307_DRAMC_DACR_PM_ON (0x0000000C) /* Continuous Page Mode */
/***********************************************************************/
/* */
/* Controls used only by Synchronous DRAM */
/* */
/***********************************************************************/
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