📄 ch7017_lfp_3364.bsf
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Page "DVO Timings"
Link "Close Table" , ".."
Table $DVO_Tbl_02 " DVO Timings Values",
Column "Timings" , 1 byte , EHEX,
Help "The DVO port timing table is compatible with EDID timing table. Please "
"look at EDID table definition to fill out this table."
"\r\n"
"\t DB ? ; Low Byte of DClk in 10 KHz\r\n"
"\t DB ? ; High Byte of DClk in 10 KHz\r\n"
"\t DB ? ; Horizontal Active in pixels, LSB\r\n"
"\t DB ? ; Horizontal Blanking in pixels, LSB\r\n"
"\t DB ? ; Bit 7-4: Upper 4 bits of Hor. Active\r\n"
" ; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
"\t DB ? ; Vertical Active in lines, LSB\r\n"
"\t DB ? ; Vertical Blanking in lines, LSB\r\n"
"\t DB ? ; Bit 7-4: Upper 4 bits of Vert. Active\r\n"
" ; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
"\t DB ? ; HSync Offset from Hor. Blanking in pix., LSB\r\n"
"\t DB ? ; HSync Pulse Width in pixels, LSB\r\n"
"\t DB ? ; Bit 7-4: Lower 4 bits of VSync Offset\r\n"
" ; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
"\t DB ? ; Bit 7-6: Upper 2 bits of HSync Offset\r\n"
" ; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
" ; Bit 3-2: Upper 2 bits of VSync Offset\r\n"
" ; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
"\t DB ? ; Horizontal Image Size, LSB\r\n"
"\t DB ? ; Vertical Image Size, LSB\r\n"
"\t DB ? ; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
" ; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
"\t DB 0 ; Horizontal Border in pixels\r\n"
"\t DB 0 ; Vertical Border in lines\r\n"
"\t DB ? ; Flags: see AIM HLD Specification\r\n"
EndPage
Page "Power Sequence"
Link "Close Table" , ".."
Table $PSQ_Tbl_02 "Power sequence registers ",
Column "Address" , 1 byte , EHEX
Column "Data" , 1 bytes , EHEX,
Help "The default register values are used for power sequence. "
"Register index, value.\r\n"
"But, you may change the contents of these registers to meet the specifications "
"of power sequence cycles of this panel.\r\n"
"Note that 6B[7:6] should be set '11'.\r\n"
"For complete settings of Power Sequence cycles, refer to the panel specifications.\r\n"
EndPage
Page "EMI Reduction(ER) Controls"
Link "Close Table" , ".."
Combo $bmp_LVDS_SS_Mode_02, "EMI Reduction Mode", &SS_Mode_List,
Help "ER can be enabled through internal or external source frequency:\r\n"
Combo $bmp_LVDS_SS_Coupling_Cap_02, "EMI Reduction Coupling Capacitor", &SS_Coupling_Cap_List,
Help "The following settings are recommended:\r\n"
"External enabled EMI Reduction mode:\r\n"
"\t\tInput MHz\tER+-0.5%~1%\tER+-1%~2%\tER+-2%~3% \r\n"
"\t\t40\t\t\t\t01h\t\t0Fh\r\n"
"\t\t65\t\t0Ah\t\t01h\t\t0Dh\r\n"
"\t\t108\t\t\t\t09h\t\t0Fh\r\n"
"\t\t162\t\t\t\t0Ah\t\t01h\r\n"
"\r\n"
;"Internal enabled EMI Reduction mode:\r\n"
;"\t\t40\t\t\t\t01h\t\t07h\r\n"
;"\t\t65\t\t\t\t04h\t\t0Ch\r\n"
;"\t\t108\t\t\t\t09h\t\t0Fh\r\n"
;"\t\t162\t\t\t\t06h\t\t09h\r\n"
EditNum $bmp_LVDS_Fre_Divider_02, "EMI Reduction Frequency Divider Ctrl (LPSSFD):", DEC,
Help " The value allowed is from 1 to 1025 in decimal. The settings below are for references:\r\n "
"External enabled EMI Reduction mode:\r\n"
"\t\tInput MHz\tLPSSFD\r\n"
"\t\t40\t\t51\r\n"
"\t\t65\t\t127\r\n"
"\t\t108\t\t150\r\n"
"\t\t162\t\t290\r\n"
"\r\n"
;"Internal enabled EMI Reduction mode:\r\n"
;"\t\t40\t\t314\r\n"
;"\t\t65\t\t403\r\n"
;"\t\t108\t\t533\r\n"
;"\t\t162\t\t625\r\n"
EditNum $bmp_LVDS_FB_Divider_02, "EMI Reduction Feed_Backward Divider Ctrl (LPSSFB): ", DEC,
Help " The value allowed is from 1 to 1025 in decimal. The settings below are for references:\r\n "
"External enabled EMI Reduction mode:\r\n"
"\t\tInput MHz\tLPSSFB\r\n"
"\t\t40\t\t7\r\n"
"\t\t65\t\t7\r\n"
"\t\t108\t\t7\r\n"
"\t\t162\t\t7\r\n"
"\r\n"
;"Internal enabled EMI Reduction mode:\r\n"
;"\t\t40\t\t10\r\n"
;"\t\t65\t\t20\r\n"
;"\t\t108\t\t15\r\n"
;"\t\t162\t\t30\r\n"
Combo $bmp_LVDS_LF_Resistor_02, "LP Resistor (Ohm) ", &SS_LF_Resistor_List,
Help "Default setting is recommended\r\n"
Combo $bmp_LVDS_SS_Resistor_02, "EMI Reduction Resistor (uA) ", &SS_Resistor_List,
Help "Default setting is recommended\r\n"
EndPage
EndPage
;============================================================================
; Page - Panel #4 LVDS Flat Panel parameters
;----------------------------------------------------------------------------
Page "Panel #4 "
Title "Flat Panel Specification, Size, and Clock"
Combo $bmp_LVDS_Panel_Spec_Select_03, "Panel Specification Select", &Panel_Spec_List,
Help "The chosen item should match the connected panel based on panel specification. "
EditNum $Panel_Width_03, "Panel Width:", DEC
EditNum $Panel_Height_03, "Panel Height:", DEC
EditNum $FP_DClk_03, "Panel Dot Clock (KHz):", DEC
Link "LVDS Parameter Table" , "LVDS Parameters"
Link "DVO Timings Table" , "DVO Timings"
Link "Power Sequence Table", "Power Sequence"
Link "EMI Reduction Table", "EMI Reduction(ER) Controls"
Page "LVDS Parameters"
Link "Close Table" , ".."
Table $LVDS_Tbl_03 " LVDS registers",
Column "Address" , 1 byte , EHEX
Column "Mask" , 1 byte, EHEX
Column "Data" , 1 byte , EHEX,
Help "The default register values are used for LVDS. "
"Register index, mask and value "
EndPage
Page "DVO Timings"
Link "Close Table" , ".."
Table $DVO_Tbl_03 " DVO Timings Values",
Column "Timings" , 1 byte , EHEX,
Help "The DVO port timing table is compatible with EDID timing table. Please "
"look at EDID table definition to fill out this table."
"\r\n"
"\t DB ? ; Low Byte of DClk in 10 KHz\r\n"
"\t DB ? ; High Byte of DClk in 10 KHz\r\n"
"\t DB ? ; Horizontal Active in pixels, LSB\r\n"
"\t DB ? ; Horizontal Blanking in pixels, LSB\r\n"
"\t DB ? ; Bit 7-4: Upper 4 bits of Hor. Active\r\n"
" ; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
"\t DB ? ; Vertical Active in lines, LSB\r\n"
"\t DB ? ; Vertical Blanking in lines, LSB\r\n"
"\t DB ? ; Bit 7-4: Upper 4 bits of Vert. Active\r\n"
" ; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
"\t DB ? ; HSync Offset from Hor. Blanking in pix., LSB\r\n"
"\t DB ? ; HSync Pulse Width in pixels, LSB\r\n"
"\t DB ? ; Bit 7-4: Lower 4 bits of VSync Offset\r\n"
" ; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
"\t DB ? ; Bit 7-6: Upper 2 bits of HSync Offset\r\n"
" ; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
" ; Bit 3-2: Upper 2 bits of VSync Offset\r\n"
" ; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
"\t DB ? ; Horizontal Image Size, LSB\r\n"
"\t DB ? ; Vertical Image Size, LSB\r\n"
"\t DB ? ; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
" ; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
"\t DB 0 ; Horizontal Border in pixels\r\n"
"\t DB 0 ; Vertical Border in lines\r\n"
"\t DB ? ; Flags: see AIM HLD Specification\r\n"
EndPage
Page "Power Sequence"
Link "Close Table" , ".."
Table $PSQ_Tbl_03 "Power sequence registers ",
Column "Address" , 1 byte , EHEX
Column "Data" , 1 bytes , EHEX,
Help "The default register values are used for power sequence. "
"Register index, value.\r\n"
"But, you may change the contents of these registers to meet the specifications "
"of power sequence cycles of this panel.\r\n"
"Note that 6B[7:6] should be set '11'.\r\n"
"For complete settings of Power Sequence cycles, refer to the panel specifications.\r\n"
EndPage
Page "EMI Reduction(ER) Controls"
Link "Close Table" , ".."
Combo $bmp_LVDS_SS_Mode_03, "EMI Reduction Mode", &SS_Mode_List,
Help "ER can be enabled through internal or external source frequency:\r\n"
Combo $bmp_LVDS_SS_Coupling_Cap_03, "EMI Reduction Coupling Capacitor", &SS_Coupling_Cap_List,
Help "The following settings are recommended:\r\n"
"External enabled EMI Reduction mode:\r\n"
"\t\tInput MHz\tER+-0.5%~1%\tER+-1%~2%\tER+-2%~3% \r\n"
"\t\t40\t\t\t\t01h\t\t0Fh\r\n"
"\t\t65\t\t0Ah\t\t01h\t\t0Dh\r\n"
"\t\t108\t\t\t\t09h\t\t0Fh\r\n"
"\t\t162\t\t\t\t0Ah\t\t01h\r\n"
"\r\n"
;"Internal enabled EMI Reduction mode:\r\n"
;"\t\t40\t\t\t\t01h\t\t07h\r\n"
;"\t\t65\t\t\t\t04h\t\t0Ch\r\n"
;"\t\t108\t\t\t\t09h\t\t0Fh\r\n"
;"\t\t162\t\t\t\t06h\t\t09h\r\n"
EditNum $bmp_LVDS_Fre_Divider_03, "EMI Reduction Frequency Divider Ctrl (LPSSFD):", DEC,
Help " The value allowed is from 1 to 1025 in decimal. The settings below are for references:\r\n "
"External enabled EMI Reduction mode:\r\n"
"\t\tInput MHz\tLPSSFD\r\n"
"\t\t40\t\t51\r\n"
"\t\t65\t\t127\r\n"
"\t\t108\t\t150\r\n"
"\t\t162\t\t290\r\n"
"\r\n"
;"Internal enabled EMI Reduction mode:\r\n"
;"\t\t40\t\t314\r\n"
;"\t\t65\t\t403\r\n"
;"\t\t108\t\t533\r\n"
;"\t\t162\t\t625\r\n"
EditNum $bmp_LVDS_FB_Divider_03, "EMI Reduction Feed_Backward Divider Ctrl (LPSSFB): ", DEC,
Help " The value allowed is from 1 to 1025 in decimal. The settings below are for references:\r\n "
"External enabled EMI Reduction mode:\r\n"
"\t\tInput MHz\tLPSSFB\r\n"
"\t\t40\t\t7\r\n"
"\t\t65\t\t7\r\n"
"\t\t108\t\t7\r\n"
"\t\t162\t\t7\r\n"
"\r\n"
;"Internal enabled EMI Reduction mode:\r\n"
;"\t\t40\t\t10\r\n"
;"\t\t65\t\t20\r\n"
;"\t\t108\t\t15\r\n"
;"\t\t162\t\t30\r\n"
Combo $bmp_LVDS_LF_Resistor_03, "LP Resistor (Ohm) ", &SS_LF_Resistor_List,
Help "Default setting is recommended\r\n"
Combo $bmp_LVDS_SS_Resistor_03, "EMI Reduction Resistor (uA) ", &SS_Resistor_List,
Help "Default setting is recommended\r\n"
EndPage
EndPage
;============================================================================
; Page - Panel #5 LVDS Flat Panel parameters
;----------------------------------------------------------------------------
Page "Panel #5 "
Title "Flat Panel Specification, Size, and Clock"
Combo $bmp_LVDS_Panel_Spec_Select_04, "Panel Specification Select", &Panel_Spec_List,
Help "The chosen item should match the connected panel based on panel specification. "
EditNum $Panel_Width_04, "Panel Width:", DEC
EditNum $Panel_Height_04, "Panel Height:", DEC
EditNum $FP_DClk_04, "Panel Dot Clock (KHz):", DEC
Link "LVDS Parameter Table" , "LVDS Parameters"
Link "DVO Timings Table" , "DVO Timings"
Link "Power Sequence Table", "Power Sequence"
Link "EMI Reduction Table", "EMI Reduction(ER) Controls"
Page "LVDS Parameters"
Link "Close Table" , ".."
Table $LVDS_Tbl_04 " LVDS registers",
Column "Address" , 1 byte , EHEX
Column "Mask" , 1 byte, EHEX
Column "Data" , 1 byte , EHEX,
Help "The default register values are used for LVDS.\r\n"
EndPage
Page "DVO Timings"
Link "Close Table" , ".."
Table $DVO_Tbl_04 " DVO Timings Values",
Column "Timings" , 1 byte , EHEX,
Help "The DVO port timing table is compatible with EDID timing table. Please "
"look at EDID table definition to fill out this table."
"\r\n"
"\t DB ? ; Low Byte of DClk in 10 KHz\r\n"
"\t DB ? ; High Byte of DClk in 10 KHz\r\n"
"\t DB ? ; Horizontal Active in pixels, LSB\r\n"
"\t DB ? ; Horizontal Blanking in pixels, LSB\r\n"
"\t DB ? ; Bit 7-4: Upper 4 bits of Hor. Active\r\n"
" ; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
"\t DB ? ; Vertical Active in lines, LSB\r\n"
"\t DB ? ; Vertical Blanking in lines, LSB\r\n"
"\t DB ? ; Bit 7-4: Upper 4 bits of Vert. Active\r\n"
" ; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
"\t DB ? ; HSync Offset from Hor. Blanking in pix., LSB\r\n"
"\t DB ? ; HSync Pulse Width in pixels, LSB\r\n"
"\t DB ? ; Bit 7-4: Lower 4 bits of VSync Offset\r\n"
" ; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
"\t DB ? ; Bit 7-6: Upper 2 bits of HSync Offset\r\n"
" ; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
" ; Bit 3-2: Upper 2 bits of VSync Offset\r\n"
" ; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
"\t DB ? ; Horizontal Image Size, LSB\r\n"
"\t DB ? ; Vertical Image Size, LSB\r\n"
"\t DB ? ; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
" ; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
"\t DB 0 ; Horizontal Border in pixels\r\n"
"\t DB 0 ; Vertical Border in lines\r\n"
"\t DB ? ; Flags: see AIM HLD Specification\r\n"
EndPage
Page "Power Sequence"
Link "Close Table" , ".."
Table $PSQ_Tbl_04 "Power sequence registers ",
Column "Address" , 1 byte , EHEX
Column "Data" , 1 bytes , EHEX,
Help "The default register values are used for power sequence. "
"Register index, value.\r\n"
"But, you may change the contents of these registers to meet the specifications "
"of power sequence cycles of this panel.\r\n"
"Note that 6B[7:6] should be set '11'.\r\n"
"For complete settings of Power Sequence cycles, refer to the panel specifications.\r\n"
EndPage
Page "EMI Reduction(ER) Controls"
Link "Close Table" , ".."
Combo $bmp_LVDS_SS_Mode_04, "EMI Reduction Mode", &SS_Mode_List,
Help "ER can be enabled through internal or external source frequency:\r\n"
Combo $bmp_LVDS_SS_Coupling_Cap_04, "EMI Reduction Coupling Capacitor", &SS_Coupling_Cap_List,
Help "The following settings are recommended:\r\n"
"External enabled EMI Reduction mode:\r\n"
"\t\tInput MHz\tER+-0.5%~1%\tER+-1%~2%\tER+-2%~3% \r\n"
"\t\t40\t\t\t\t01h\t\t0Fh\r\n"
"\t\t65\t\t0Ah\t\t01h\t\t0Dh\r\n"
"\t\t108\t\t\t\t09h\t\t0Fh\r\n"
"\t\t162\t\t\t\t0Ah\t\t01h\r\n"
"\r\n"
;"Internal enabled EMI Reduction mode:\r\n"
;"\t\t40\t\t\t\t01h\t\t07h\r\n"
;"\t\t65\t\t\t\t04h\t\t0Ch\r\n"
;"\t\t108\t\t\t\t09h\t\t0Fh\r\n"
;"\t\t162\t\t\t\t06h\t\t09h\r\n"
EditNum $bmp_LVDS_Fre_Divider_04, "EMI Reduction Frequency Divider Ctrl (LPSSFD):", DEC,
Help " The value allowed is from 1 to 1025 in decimal. The settings below are for references:\r\n "
"External enabled EMI Reduction mode:\r\n"
"\t\tInput MHz\tLPSSFD\r\n"
"\t\t40\t\t51\r\n"
"\t\t65\t\t127\r\n"
"\t\t108\t\t150\r\n"
"\t\t162\t\t290\r\n"
"\r\n"
;"Internal enabled EMI Reduction mode:\r\n"
;"\t\t40\t\t314\r\n"
;"\t\t65\t\t403\r\n"
;"\t\t108\t\t533\r\n"
;"\t\t162\t\t625\r\n"
EditNum $bmp_LVDS_FB_Divider_04, "EMI Reduction Feed_Backward Divider Ctrl (LPSSFB): ", DEC,
Help " The value allowed is from 1 to 1025 in decimal. The settings below are for references:\r\n "
"External enabled EMI Reduction mode:\r\n"
"\t\tInput MHz\tLPSSFB\r\n"
"\t\t40\t\t7\r\n"
"\t\t65\t\t7\r\n"
"\t\t108\t\t7\r\n"
"\t\t162\t\t7\r\n"
"\r\n"
;"Internal enabled EMI Reduction mode:\r\n"
;"\t\t40\t\t10\r\n"
;"\t\t65\t\t20\r\n"
;"\t\t108\t\t15\r\n"
;"\t\t162\t\t30\r\n"
Combo $bmp_LVDS_LF_Resistor_04, "LP Resistor (Ohm) ", &SS_LF_Resistor_List,
Help "Default setting is recommended\r\n"
Combo $bmp_LVDS_SS_Resistor_04, "EMI Reduction Resistor (uA) ", &SS_Resistor_List,
Help "Default setting is recommended\r\n"
EndPage
EndPage
;============================================================================
; End of File
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