📄 ch7017_lfp_3364.bsf
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;============================================================================
; Page - Message Options
;----------------------------------------------------------------------------
;============================================================================
; Page - LVDS Features
;----------------------------------------------------------------------------
Page "LVDS Display Configuration"
;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; commented out by JD, 08/21/02
;Link "EMI Reduction Settings" , "EMI Reduction(ER) Controls"
;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Combo $bmp_Panel_type, "Select Panel Type:", &Panel_List,
Help "If a 'Panel #?' is selected, the BIOS will boot to that "
"panel. This can be overridden by a INT 15(to 5F40h) call. "
"The panel number is 1-based meaning it starts with number 1.\r\n"
"\r\n"
"If 'Read HW Pins' is selected, the BIOS will boot with the "
"panel number read from GPIO pins [5:2]. This can be overridden "
"by a INT 15 (to 5F40h) call also.\r\n"
"You may assign each panel # to a panel type you desire. \r\n"
"But be mindful that the list of panels is indexed as follows:\r\n"
" \tReturn value 0 refers to Panel#1\r\n"
" \tReturn value 1 refers to Panel#2\r\n"
" \tReturn value 2 refers to Panel#3\r\n"
" \tReturn value 3 refers to Panel#4\r\n"
" \tReturn value 4 refers to Panel#5\r\n"
"\r\n"
"Please, any return value from 5F40h should be less than or equal to 4."
Combo $bmp_H40_Set_Panel_Type, "5F40h - Panel Type Hook:", &IntSys_List,
Help "The video BIOS will call INT 15h, or"
" Disabled.\r\n"
"\r\n"
"Be cautious that any return value greater than 4 is invalid and \r\n"
"Panel#2 is set as default panel type.\r\n"
"\r\n"
"when either INT 15 (to 5F40h) or CHRONTEL GPIO[5:2] configuration is made.\r\n"
"The list of panels is indexed as follows: \r\n"
" \tReturn value 0 refers to Panel#1\r\n"
" \tReturn value 1 refers to Panel#2\r\n"
" \tReturn value 2 refers to Panel#3\r\n"
" \tReturn value 3 refers to Panel#4\r\n"
" \tReturn value 4 refers to Panel#5\r\n"
"\r\n"
"If INT 15 call fails, default panel type is selected from the 'Select Panel Type' menu.\r\n"
"If 'Read HW Pin' is selected, Chrontel GPIO[5:2] determines the panel type.\r\n"
"\r\n"
"If you select 'Disabled', no INT 15 call is made.\r\n"
"Instead a panel type is selected from the 'Select Panel Type' menu.\r\n"
Combo $bmp_LVDS_BAddr, "Set LVDS I2C Slave Address:", &LVDS_BAddr_List,
Help "The Slave Address, which is used for the LVDS registers programming, are as follows:\r\n"
" \r\n"
" \tCH7017: EAh\r\n"
" \tCH7018: EAh\r\n"
" \tCH7019: EAh\r\n"
" \tCH7020: EAh\r\n"
" \tCH7302: ECh\r\n"
Combo $bmp_LVDS_Capabilities, "LVDS Capabilities:", &Capabilities_List,
Help "The screen is centered with borders in No Up-Scaling mode. \r\n"
"The screen is filled up with no borders in Up-Scaling mode."
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Comment out by JD, 09/17/02
;Combo $bmp_LVDS_Panel_Spec_Select, "Panel Specification Select", &Panel_Spec_List,
;Help "The chosen item should match the connected panel based on panel specification. "
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
EndPage
;============================================================================
; Page - LVDS Boot Register Table
;----------------------------------------------------------------------------
;============================================================================
; Page - Panel #1 LVDS Flat Panel parameters
;----------------------------------------------------------------------------
Page "Panel #1 "
Title "Flat Panel Specification, Size, and Clock"
Combo $bmp_LVDS_Panel_Spec_Select_00, "Panel Specification Select", &Panel_Spec_List,
Help "The chosen item should match the connected panel based on panel specification. "
EditNum $Panel_Width_00, "Panel Width:", DEC
EditNum $Panel_Height_00, "Panel Height:", DEC
EditNum $FP_DClk_00, "Panel Dot Clock (KHz):", DEC
Link "LVDS Parameter Table" , "LVDS Parameters"
Link "DVO Timings Table" , "DVO Timings"
Link "Power Sequence Table", "Power Sequence"
Link "EMI Reduction Table", "EMI Reduction(ER) Controls"
Page "LVDS Parameters"
Link "Close Table" , ".."
Table $LVDS_Tbl_00 " LVDS registers",
Column "Address" , 1 byte , EHEX
Column "Mask" , 1 byte, EHEX
Column "Data" , 1 byte , EHEX,
Help "The default register values are used for LVDS. "
"Register index, mask and value "
EndPage
Page "DVO Timings"
Link "Close Table" , ".."
Table $DVO_Tbl_00 " DVO Timings Values",
Column "Timings" , 1 byte , EHEX,
Help "The DVO port timing table is compatible with EDID timing table. Please "
"look at EDID table definition to fill out this table."
"\r\n"
"\t DB ? ; Low Byte of DClk in 10 KHz\r\n"
"\t DB ? ; High Byte of DClk in 10 KHz\r\n"
"\t DB ? ; Horizontal Active in pixels, LSB\r\n"
"\t DB ? ; Horizontal Blanking in pixels, LSB\r\n"
"\t DB ? ; Bit 7-4: Upper 4 bits of Hor. Active\r\n"
" ; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
"\t DB ? ; Vertical Active in lines, LSB\r\n"
"\t DB ? ; Vertical Blanking in lines, LSB\r\n"
"\t DB ? ; Bit 7-4: Upper 4 bits of Vert. Active\r\n"
" ; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
"\t DB ? ; HSync Offset from Hor. Blanking in pix., LSB\r\n"
"\t DB ? ; HSync Pulse Width in pixels, LSB\r\n"
"\t DB ? ; Bit 7-4: Lower 4 bits of VSync Offset\r\n"
" ; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
"\t DB ? ; Bit 7-6: Upper 2 bits of HSync Offset\r\n"
" ; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
" ; Bit 3-2: Upper 2 bits of VSync Offset\r\n"
" ; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
"\t DB ? ; Horizontal Image Size, LSB\r\n"
"\t DB ? ; Vertical Image Size, LSB\r\n"
"\t DB ? ; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
" ; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
"\t DB 0 ; Horizontal Border in pixels\r\n"
"\t DB 0 ; Vertical Border in lines\r\n"
"\t DB ? ; Flags: see AIM HLD Specification\r\n"
EndPage
Page "Power Sequence"
Link "Close Table" , ".."
Table $PSQ_Tbl_00 "Power sequence registers ",
Column "Address" , 1 byte , EHEX
Column "Data" , 1 bytes , EHEX,
Help "The default register values are used for power sequence. "
"Register index, value.\r\n"
"But, you may change the contents of these registers to meet the specifications "
"of power sequence cycles of this panel.\r\n"
"Note that 6B[7:6] should be set '11'.\r\n"
"For complete settings of Power Sequence cycles, refer to the panel specifications.\r\n"
EndPage
Page "EMI Reduction(ER) Controls"
Link "Close Table" , ".."
Combo $bmp_LVDS_SS_Mode_00, "EMI Reduction Mode", &SS_Mode_List,
Help "ER can be enabled through internal or external source frequency:\r\n"
Combo $bmp_LVDS_SS_Coupling_Cap_00, "EMI Reduction Coupling Capacitor", &SS_Coupling_Cap_List,
Help "The following settings are recommended:\r\n"
"External enabled EMI Reduction mode:\r\n"
"\t\tInput MHz\tER+-0.5%~1%\tER+-1%~2%\tER+-2%~3% \r\n"
"\t\t40\t\t\t\t01h\t\t0Fh\r\n"
"\t\t65\t\t0Ah\t\t01h\t\t0Dh\r\n"
"\t\t108\t\t\t\t09h\t\t0Fh\r\n"
"\t\t162\t\t\t\t0Ah\t\t01h\r\n"
"\r\n"
;"Internal enabled EMI Reduction mode:\r\n"
;"\t\t40\t\t\t\t01h\t\t07h\r\n"
;"\t\t65\t\t\t\t04h\t\t0Ch\r\n"
;"\t\t108\t\t\t\t09h\t\t0Fh\r\n"
;"\t\t162\t\t\t\t06h\t\t09h\r\n"
EditNum $bmp_LVDS_Fre_Divider_00, "EMI Reduction Frequency Divider Ctrl (LPSSFD):", DEC,
Help " The value allowed is from 1 to 1025 in decimal. The settings below are for references:\r\n "
"External enabled EMI Reduction mode:\r\n"
"\t\tInput MHz\tLPSSFD\r\n"
"\t\t40\t\t51\r\n"
"\t\t65\t\t127\r\n"
"\t\t108\t\t150\r\n"
"\t\t162\t\t290\r\n"
"\r\n"
;"Internal enabled EMI Reduction mode:\r\n"
;"\t\t40\t\t314\r\n"
;"\t\t65\t\t403\r\n"
;"\t\t108\t\t533\r\n"
;"\t\t162\t\t625\r\n"
EditNum $bmp_LVDS_FB_Divider_00, "EMI Reduction Feed_Backward Divider Ctrl (LPSSFB): ", DEC,
Help " The value allowed is from 1 to 1025 in decimal. The settings below are for references:\r\n "
"External enabled EMI Reduction mode:\r\n"
"\t\tInput MHz\tLPSSFB\r\n"
"\t\t40\t\t7\r\n"
"\t\t65\t\t7\r\n"
"\t\t108\t\t7\r\n"
"\t\t162\t\t7\r\n"
"\r\n"
;"Internal enabled EMI Reduction mode:\r\n"
;"\t\t40\t\t10\r\n"
;"\t\t65\t\t20\r\n"
;"\t\t108\t\t15\r\n"
;"\t\t162\t\t30\r\n"
Combo $bmp_LVDS_LF_Resistor_00, "LP Resistor (Ohm) ", &SS_LF_Resistor_List,
Help "Default setting is recommended\r\n"
Combo $bmp_LVDS_SS_Resistor_00, "EMI Reduction Resistor (uA) ", &SS_Resistor_List,
Help "Default setting is recommended\r\n"
EndPage
EndPage
;============================================================================
; Page - Panel #2 LVDS Flat Panel parameters
;----------------------------------------------------------------------------
Page "Panel #2 "
Title "Flat Panel Specification, Size, and Clock"
Combo $bmp_LVDS_Panel_Spec_Select_01, "Panel Specification Select", &Panel_Spec_List,
Help "The chosen item should match the connected panel based on panel specification. "
EditNum $Panel_Width_01, "Panel Width:", DEC
EditNum $Panel_Height_01, "Panel Height:", DEC
EditNum $FP_DClk_01, "Panel Dot Clock (KHz):", DEC
Link "LVDS Parameter Table" , "LVDS Parameters"
Link "DVO Timings Table" , "DVO Timings"
Link "Power Sequence Table", "Power Sequence"
Link "EMI Reduction Table", "EMI Reduction(ER) Controls"
Page "LVDS Parameters"
Link "Close Table" , ".."
Table $LVDS_Tbl_01 " LVDS registers",
Column "Address" , 1 byte , EHEX
Column "Mask" , 1 byte, EHEX
Column "Data" , 1 byte , EHEX,
Help "The default register values are used for LVDS. "
"Register index, mask and value "
EndPage
Page "DVO Timings"
Link "Close Table" , ".."
Table $DVO_Tbl_01 " DVO Timings Values",
Column "Timings" , 1 byte , EHEX,
Help "The DVO port timing table is compatible with EDID timing table. Please "
"look at EDID table definition to fill out this table."
"\r\n"
"\t DB ? ; Low Byte of DClk in 10 KHz\r\n"
"\t DB ? ; High Byte of DClk in 10 KHz\r\n"
"\t DB ? ; Horizontal Active in pixels, LSB\r\n"
"\t DB ? ; Horizontal Blanking in pixels, LSB\r\n"
"\t DB ? ; Bit 7-4: Upper 4 bits of Hor. Active\r\n"
" ; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n"
"\t DB ? ; Vertical Active in lines, LSB\r\n"
"\t DB ? ; Vertical Blanking in lines, LSB\r\n"
"\t DB ? ; Bit 7-4: Upper 4 bits of Vert. Active\r\n"
" ; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n"
"\t DB ? ; HSync Offset from Hor. Blanking in pix., LSB\r\n"
"\t DB ? ; HSync Pulse Width in pixels, LSB\r\n"
"\t DB ? ; Bit 7-4: Lower 4 bits of VSync Offset\r\n"
" ; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n"
"\t DB ? ; Bit 7-6: Upper 2 bits of HSync Offset\r\n"
" ; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n"
" ; Bit 3-2: Upper 2 bits of VSync Offset\r\n"
" ; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n"
"\t DB ? ; Horizontal Image Size, LSB\r\n"
"\t DB ? ; Vertical Image Size, LSB\r\n"
"\t DB ? ; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n"
" ; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n"
"\t DB 0 ; Horizontal Border in pixels\r\n"
"\t DB 0 ; Vertical Border in lines\r\n"
"\t DB ? ; Flags: see AIM HLD Specification\r\n"
EndPage
Page "Power Sequence"
Link "Close Table" , ".."
Table $PSQ_Tbl_01 "Power sequence registers ",
Column "Address" , 1 byte , EHEX
Column "Data" , 1 bytes , EHEX,
Help "The default register values are used for power sequence. "
"Register index, value.\r\n"
"But, you may change the contents of these registers to meet the specifications "
"of power sequence cycles of this panel.\r\n"
"Note that 6B[7:6] should be set '11'.\r\n"
"For complete settings of Power Sequence cycles, refer to the panel specifications.\r\n"
EndPage
Page "EMI Reduction(ER) Controls"
Link "Close Table" , ".."
Combo $bmp_LVDS_SS_Mode_01, "EMI Reduction Mode", &SS_Mode_List,
Help "ER can be enabled through internal or external source frequency:\r\n"
Combo $bmp_LVDS_SS_Coupling_Cap_01, "EMI Reduction Coupling Capacitor", &SS_Coupling_Cap_List,
Help "The following settings are recommended:\r\n"
"External enabled EMI Reduction mode:\r\n"
"\t\tInput MHz\tER+-0.5%~1%\tER+-1%~2%\tER+-2%~3% \r\n"
"\t\t40\t\t\t\t01h\t\t0Fh\r\n"
"\t\t65\t\t0Ah\t\t01h\t\t0Dh\r\n"
"\t\t108\t\t\t\t09h\t\t0Fh\r\n"
"\t\t162\t\t\t\t0Ah\t\t01h\r\n"
"\r\n"
;"Internal enabled EMI Reduction mode:\r\n"
;"\t\t40\t\t\t\t01h\t\t07h\r\n"
;"\t\t65\t\t\t\t04h\t\t0Ch\r\n"
;"\t\t108\t\t\t\t09h\t\t0Fh\r\n"
;"\t\t162\t\t\t\t06h\t\t09h\r\n"
EditNum $bmp_LVDS_Fre_Divider_01, "EMI Reduction Frequency Divider Ctrl (LPSSFD):", DEC,
Help " The value allowed is from 1 to 1025 in decimal. The settings below are for references:\r\n "
"External enabled EMI Reduction mode:\r\n"
"\t\tInput MHz\tLPSSFD\r\n"
"\t\t40\t\t51\r\n"
"\t\t65\t\t127\r\n"
"\t\t108\t\t150\r\n"
"\t\t162\t\t290\r\n"
"\r\n"
;"Internal enabled EMI Reduction mode:\r\n"
;"\t\t40\t\t314\r\n"
;"\t\t65\t\t403\r\n"
;"\t\t108\t\t533\r\n"
;"\t\t162\t\t625\r\n"
EditNum $bmp_LVDS_FB_Divider_01, "EMI Reduction Feed_Backward Divider Ctrl (LPSSFB): ", DEC,
Help " The value allowed is from 1 to 1025 in decimal. The settings below are for references:\r\n "
"External enabled EMI Reduction mode:\r\n"
"\t\tInput MHz\tLPSSFB\r\n"
"\t\t40\t\t7\r\n"
"\t\t65\t\t7\r\n"
"\t\t108\t\t7\r\n"
"\t\t162\t\t7\r\n"
"\r\n"
;"Internal enabled EMI Reduction mode:\r\n"
;;"\t\t40\t\t10\r\n"
;"\t\t65\t\t20\r\n"
;"\t\t108\t\t15\r\n"
;"\t\t162\t\t30\r\n"
Combo $bmp_LVDS_LF_Resistor_01, "LP Resistor (Ohm) ", &SS_LF_Resistor_List,
Help "Default setting is recommended\r\n"
Combo $bmp_LVDS_SS_Resistor_01, "EMI Reduction Resistor (uA) ", &SS_Resistor_List,
Help "Default setting is recommended\r\n"
EndPage
EndPage
;============================================================================
; Page - Panel #3 LVDS Flat Panel parameters
;----------------------------------------------------------------------------
Page "Panel #3 "
Title "Flat Panel Specification, Size, and Clock"
Combo $bmp_LVDS_Panel_Spec_Select_02, "Panel Specification Select", &Panel_Spec_List,
Help "The chosen item should match the connected panel based on panel specification. "
EditNum $Panel_Width_02, "Panel Width:", DEC
EditNum $Panel_Height_02, "Panel Height:", DEC
EditNum $FP_DClk_02, "Panel Dot Clock (KHz):", DEC
Link "LVDS Parameter Table" , "LVDS Parameters"
Link "DVO Timings Table" , "DVO Timings"
Link "Power Sequence Table", "Power Sequence"
Link "EMI Reduction Table", "EMI Reduction(ER) Controls"
Page "LVDS Parameters"
Link "Close Table" , ".."
Table $LVDS_Tbl_02 " LVDS registers",
Column "Address" , 1 byte , EHEX
Column "Mask" , 1 byte, EHEX
Column "Data" , 1 byte , EHEX,
Help "The default register values are used for LVDS. "
"Register index, mask and value "
EndPage
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