📄 ch7017_lfp_3364.bsf
字号:
; TITLE LVDS7017.bsf - BMP Scrip File for Intel LVDS flat panel controller
;============================================================================
; Advance Graphics ROM BIOS
;----------------------------------------------------------------------------
; Copyright (c) Intel Corporation (1999).
;
; INTEL MAKES NO WARRANTY OF ANY KIND REGARDING THE CODE. THIS CODE IS
; LICENSED ON AN "AS IS" BASIS AND INTEL WILL NOT PROVIDE ANY SUPPORT,
; ASSISTANCE, INSTALLATION, TRAINING OR OTHER SERVICES.
; INTEL DOES NOT PROVIDE ANY UPDATES, ENHANCEMENTS OR EXTENSIONS.
; INTEL SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY,
; NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY OTHER
; WARRANTY.
;
; Intel disclaims all liability, including liability for infringement of
; any proprietary rights, relating to use of the code. No license, express
; or implied, by estoppel or otherwise, to any intellectual property rights
; is granted herein.
;
; File Description:
; This file is the script file use by the BMP utility which will allow
; OEM's to edit data and select features on a binary file.
;
; History :
; 09/16/02 JD Re-organzie the pages.
; Remove the general ER settings page, and add ER settings page to each panel type.
; 08/23/02 XL Support only External EMI Reduction settings.
; 08/23/02 XL Support 5 panel types
; 08/23/02 XL Revise Help section.
; 08/01/02 JD Add ER resistor for ER setting
; 07/30/02 dk Add ER LP resistor For ER setting
; 07/08/02 dk Update 15 bytes in pointer variables $LVDS_Tbl_xx to 18 bytes because of adding one register
; skip 19 bytes instead of 16 bytes
; 06/03/02 dk Add Panel Spec. Select, TV/LVDS data path select and ER controls
; 05/03/02 dk Change $LVDS_Tbl_Size_xx to 15 bytes in pointer variables $LVDS_Tbl_xx to avoid gabage content
; 04/22/02 LLh Add table B and C back to all supported panel to let OEM change the values
; 02/27/02 LLH Do not use hook for delay frames, comment out the frames list. Add panel entry #5 16*12 back
; 02/13/02 LLH Borrow panel hook for delay # frame and add entries, Add VR64 to table A
; 02/05/02 LLH Use Table C as power sequence for each panel type
; Xiu_Chuan add some help information
; 01/29/02 LLH Update table and BMP script
; 01/07/02 LLH Add capabilities into LVDS display configuration
; 01/05/02 LLH Support 6 panel types 00- 05 based on Xiu-Chung 12/11/01 version
;
; Version Control:
; $Revision: 38 $
; $Date: 10/21/00 4:53p $
;
;----------------------------------------------------------------------------
;============================================================================
; Start of LVDS BMP Structure Definition
;----------------------------------------------------------------------------
StructDef
Find "BMP_7017_Start "
Find_Ptr_Ref "BMP_7017_Start "
SKIP 26 bytes
;============================================================================
; LVDS BIOS Data Block #1
SKIP 3 bytes ; Skip ID
$bmp_Panel_type 1 byte ; Flat panel type
$bmp_H40_Set_Panel_Type 1 byte ; Panel type hook int vector
$bmp_LVDS_BAddr 1 byte ; LVDS default slave address
$bmp_LVDS_Capabilities 1 byte ; LVDS capability byte
$bmp_LVDS_Panel_Spec_Select 1 byte ; Panel Spec selection OpenLDI/SPWG
$bmp_LVDS_TV_Datapath 1 byte ; LVDS/TV data path
$bmp_LVDS_SS_Mode 1 byte ; ER mode
$bmp_LVDS_SS_Coupling_Cap 1 byte ;
$bmp_LVDS_Fre_Divider 2 bytes ;
$bmp_LVDS_FB_Divider 2 bytes ;
$bmp_LVDS_LF_Resistor 1 byte ;
$bmp_LVDS_SS_Resistor 1 byte ;
;============================================================================
; LVDS BIOS data block #2
SKIP 3 bytes ; SKIP ID
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; comment out by JD, 09/17/02
;$LVDS_Reset_Table_Ptr 2 bytes ; Start at BMP Boot table
;$LVDS_Reset_Table_Size 2 bytes
;$LVDS_Reset_Table, $LVDS_Reset_Table_Ptr, $LVDS_Reset_Table_Size, Offset 0 bytes
;
;SKIP 31 bytes ; Skip LVDS reset table body
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;=============================================================================
; LVDS BIOS data block #3
; BMP Flat Panel data tables pointers
SKIP 3 bytes ; SKIP ID
$LVDS_Tbl_Ptr_00 2 bytes
$LVDS_Tbl_Size_00 1 byte
$LVDS_Tbl_00, $LVDS_Tbl_Ptr_00, 18 bytes, Offset 8 bytes
$DVO_Tbl_Ptr_00 2 bytes
$DVO_Tbl_Size_00 1 byte
$DVO_Tbl_00, $DVO_Tbl_Ptr_00, $DVO_Tbl_Size_00, Offset 0 byte
$PSQ_Tbl_Ptr_00 2 bytes
$PSQ_Tbl_Size_00 1 byte
$PSQ_Tbl_00, $PSQ_Tbl_Ptr_00, $PSQ_Tbl_Size_00, Offset 0 bytes
$LVDS_Tbl_Ptr_01 2 bytes
$LVDS_Tbl_Size_01 1 byte
$LVDS_Tbl_01, $LVDS_Tbl_Ptr_01, 18 bytes, Offset 8 bytes
$DVO_Tbl_Ptr_01 2 bytes
$DVO_Tbl_Size_01 1 byte
$DVO_Tbl_01, $DVO_Tbl_Ptr_01, $DVO_Tbl_Size_01, Offset 0 byte
$PSQ_Tbl_Ptr_01 2 bytes
$PSQ_Tbl_Size_01 1 byte
$PSQ_Tbl_01, $PSQ_Tbl_Ptr_01, $PSQ_Tbl_Size_01, Offset 0 bytes
$LVDS_Tbl_Ptr_02 2 bytes
$LVDS_Tbl_Size_02 1 byte
$LVDS_Tbl_02, $LVDS_Tbl_Ptr_02, 18 bytes, Offset 8 bytes
$DVO_Tbl_Ptr_02 2 bytes
$DVO_Tbl_Size_02 1 byte
$DVO_Tbl_02, $DVO_Tbl_Ptr_02, $DVO_Tbl_Size_02, Offset 0 byte
$PSQ_Tbl_Ptr_02 2 bytes
$PSQ_Tbl_Size_02 1 byte
$PSQ_Tbl_02, $PSQ_Tbl_Ptr_02, $PSQ_Tbl_Size_02, Offset 0 bytes
$LVDS_Tbl_Ptr_03 2 bytes
$LVDS_Tbl_Size_03 1 byte
$LVDS_Tbl_03, $LVDS_Tbl_Ptr_03, 18 bytes, Offset 8 bytes
$DVO_Tbl_Ptr_03 2 bytes
$DVO_Tbl_Size_03 1 byte
$DVO_Tbl_03, $DVO_Tbl_Ptr_03, $DVO_Tbl_Size_03, Offset 0 byte
$PSQ_Tbl_Ptr_03 2 bytes
$PSQ_Tbl_Size_03 1 byte
$PSQ_Tbl_03, $PSQ_Tbl_Ptr_03, $PSQ_Tbl_Size_03, Offset 0 bytes
$LVDS_Tbl_Ptr_04 2 bytes
$LVDS_Tbl_Size_04 1 byte
$LVDS_Tbl_04, $LVDS_Tbl_Ptr_04, 18 bytes, Offset 8 bytes
$DVO_Tbl_Ptr_04 2 bytes
$DVO_Tbl_Size_04 1 byte
$DVO_Tbl_04, $DVO_Tbl_Ptr_04, $DVO_Tbl_Size_04, Offset 0 byte
$PSQ_Tbl_Ptr_04 2 bytes
$PSQ_Tbl_Size_04 1 byte
$PSQ_Tbl_04, $PSQ_Tbl_Ptr_04, $PSQ_Tbl_Size_04, Offset 0 bytes
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Add by JD, 09/17/02
SKIP 44 bytes
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;==============================================================================
; LVDS BIOS data block #4
SKIP 3 bytes ; SKIP ID
; be careful the index number, for code starting from 0, for user interface starting from 1
; Flat Panel #1
$Panel_Width_00 2 bytes ; Panel Width
$Panel_Height_00 2 bytes ; Panel Height
$FP_DClk_00 4 bytes ; FP Dot Clock
SKIP 19 bytes ; FP parameters, used to 13
SKIP 18 bytes ; DTD
SKIP 10 bytes ; Power sequence
; Flat Panel #1
$Panel_Width_01 2 bytes ; Panel Width
$Panel_Height_01 2 bytes ; Panel Height
$FP_DClk_01 4 bytes ; FP Dot Clock
SKIP 19 bytes ; FP parameters
SKIP 18 bytes ; DTD
SKIP 10 bytes ; Power sequence
; Flat Panel #2
$Panel_Width_02 2 bytes ; Panel Width
$Panel_Height_02 2 bytes ; Panel Height
$FP_DClk_02 4 bytes ; FP Dot Clock
SKIP 19 bytes ; FP parameters
SKIP 18 bytes ; DTD
SKIP 10 bytes ; Power sequence
; Flat Panel #3
$Panel_Width_03 2 bytes ; Panel Width
$Panel_Height_03 2 bytes ; Panel Height
$FP_DClk_03 4 bytes ; FP Dot Clock
SKIP 19 bytes ; FP parameters
SKIP 18 bytes ; DTD
SKIP 10 bytes ; Power sequence
; Flat Panel #4
$Panel_Width_04 2 bytes ; Panel Width
$Panel_Height_04 2 bytes ; Panel Height
$FP_DClk_04 4 bytes ; FP Dot Clock
SKIP 19 bytes ; FP parameters
SKIP 18 bytes ; DTD
SKIP 10 bytes ; Power sequence
;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Add by JD, 09/16/02
$bmp_LVDS_Panel_Spec_Select_00 1 byte ; Panel Spec selection OpenLDI/SPWG
$bmp_LVDS_SS_Mode_00 1 byte ;
$bmp_LVDS_SS_Coupling_Cap_00 1 byte ;
$bmp_LVDS_Fre_Divider_00 2 bytes ;
$bmp_LVDS_FB_Divider_00 2 bytes ;
$bmp_LVDS_LF_Resistor_00 1 byte ;
$bmp_LVDS_SS_Resistor_00 1 byte ;
$bmp_LVDS_Panel_Spec_Select_01 1 byte ; Panel Spec selection OpenLDI/SPWG
$bmp_LVDS_SS_Mode_01 1 byte ;
$bmp_LVDS_SS_Coupling_Cap_01 1 byte ;
$bmp_LVDS_Fre_Divider_01 2 bytes ;
$bmp_LVDS_FB_Divider_01 2 bytes ;
$bmp_LVDS_LF_Resistor_01 1 byte ;
$bmp_LVDS_SS_Resistor_01 1 byte ;
$bmp_LVDS_Panel_Spec_Select_02 1 byte ; Panel Spec selection OpenLDI/SPWG
$bmp_LVDS_SS_Mode_02 1 byte ;
$bmp_LVDS_SS_Coupling_Cap_02 1 byte ;
$bmp_LVDS_Fre_Divider_02 2 bytes ;
$bmp_LVDS_FB_Divider_02 2 bytes ;
$bmp_LVDS_LF_Resistor_02 1 byte ;
$bmp_LVDS_SS_Resistor_02 1 byte ;
$bmp_LVDS_Panel_Spec_Select_03 1 byte ; Panel Spec selection OpenLDI/SPWG
$bmp_LVDS_SS_Mode_03 1 byte ;
$bmp_LVDS_SS_Coupling_Cap_03 1 byte ;
$bmp_LVDS_Fre_Divider_03 2 bytes ;
$bmp_LVDS_FB_Divider_03 2 bytes ;
$bmp_LVDS_LF_Resistor_03 1 byte ;
$bmp_LVDS_SS_Resistor_03 1 byte ;
$bmp_LVDS_Panel_Spec_Select_04 1 byte ; Panel Spec selection OpenLDI/SPWG
$bmp_LVDS_SS_Mode_04 1 byte ;
$bmp_LVDS_SS_Coupling_Cap_04 1 byte ;
$bmp_LVDS_Fre_Divider_04 2 bytes ;
$bmp_LVDS_FB_Divider_04 2 bytes ;
$bmp_LVDS_LF_Resistor_04 1 byte ;
$bmp_LVDS_SS_Resistor_04 1 byte ;
SKIP 10 bytes
;+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
EndStruct
;============================================================================
; LVDS List Definitions
;----------------------------------------------------------------------------
List &Panel_List
Selection 0x00, "PANEL #01"
Selection 0x01, "PANEL #02"
Selection 0x02, "PANEL #03"
Selection 0x03, "PANEL #04"
Selection 0x04, "PANEL #05"
Selection 0x80, "Read HW Pins"
EndList
List &IntSys_List
Selection 0x00, "Disabled"
Selection 0x01, "USE INT 15H"
EndList
; temp save for later delay use --- maybe... 022702
;List &IntSys_List
; Selection 0x00, "Disabled"
; Selection 0x05, "5 frames"
;...
; Selection 0xFA, "250 frames"
;EndList
;--- end temp
List &LVDS_BAddr_List
Selection 0x00, "No I2C Support"
Selection 0xEA, "EAh"
Selection 0xEC, "ECh"
EndList
;List &LVDS_GPIO_List
; Selection 0x00, "LVDS GPIO Pin #0"
; Selection 0x01, "LVDS GPIO Pin #1"
; Selection 0x06, "LVDS GPIO Pin #6"
;EndList
List &Capabilities_List
Selection 0x24, "No Up-Scaling"
Selection 0x27, "Up Scaling"
EndList
List &Master_Panel_List
Selection 0x00, "640x480 TFT"
Selection 0x01, "800x600 TFT"
Selection 0x02, "1024x768 TFT"
Selection 0x03, "1280x1024 TFT"
Selection 0x04, "1400x1050 TFT"
Selection 0x05, "1600x1200 TFT"
; Selection 0x06, "1024x768 TFT"
; Selection 0x07, "1024x768 TFT"
; Selection 0x08, "1024x768 TFT"
; Selection 0x09, "1024x768 TFT"
; Selection 0x0A, "1024x768 TFT"
; Selection 0x0B, "1024x768 TFT"
; Selection 0x0C, "1024x768 TFT"
; Selection 0x0D, "1024x768 TFT"
; Selection 0x0E, "1024x768 TFT"
; Selection 0x0F, "1024x768 TFT"
EndList
List &Panel_Spec_List
Selection 0x00, "OpenLDI\SPWG + 18 bit output"
Selection 0x01, "OpenLDI + 24 bit output"
Selection 0x02, "SPWG + 24 bit output"
EndList
List &Datapath_List
Selection 0x01, "DVOB(D1) to LVDS and DVOC(D2) to TV"
Selection 0x02, "DVOB(D1) to TV and DVOC(D2) to LVDS"
EndList
List &SS_Mode_List
;Selection 0x00, "ER enabled through internal source"
Selection 0x01, "ER enabled through external source"
EndList
List &SS_Coupling_Cap_List
Selection 0x00, "00h"
Selection 0x01, "01h"
Selection 0x02, "02h"
Selection 0x03, "03h"
Selection 0x04, "04h"
Selection 0x05, "05h"
Selection 0x06, "06h"
Selection 0x07, "07h"
Selection 0x08, "08h"
Selection 0x09, "09h"
Selection 0x0A, "0Ah"
Selection 0x0B, "0Bh"
Selection 0x0C, "0Ch"
Selection 0x0D, "0Dh"
Selection 0x0E, "0Eh"
Selection 0x0F, "0Fh"
EndList
List &SS_LF_Resistor_List
Selection 0x00, "1800"
Selection 0x01, "2600"
Selection 0x02, "1000"
Selection 0x03, "3200"
Selection 0x04, "21,800"
Selection 0x05, "42,600"
Selection 0x06, "11,000"
Selection 0x07, "73,200"
EndList
List &SS_Resistor_List
Selection 0x00, "0"
Selection 0x01, "10"
Selection 0x02, "20"
Selection 0x04, "40"
Selection 0x05, "50"
Selection 0x06, "60"
Selection 0x07, "70"
EndList
;============================================================================
; Page Definitions
;----------------------------------------------------------------------------
BeginInfoBlock
PPVer 1
Image 0 Thru EOF At EOF
EndInfoBlock
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -