📄 rominit.s
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/* romInit.s - HaeDong HD860-R3 ROM initialization module */
/* Copyright 2000 HaeDong Information & Communications Co.,Ltd. */
/*
modification history
--------------------
2000/3/16 create ykahn
*/
/*********************************/
/* Include files */
/*********************************/
#define _ASMLANGUAGE
#include "vxWorks.h"
#include "asm.h"
#include "config.h"
#include "regs.h"
#include "sysLib.h"
#include "drv/multi/ppc860Siu.h"
#include "hd860r3.h"
/********************************/
/* Global routines defined here */
/********************************/
.globl _romInit
.globl romInit
/********************************/
/* External routines called */
/********************************/
.extern romStart
/****************************************************************************/
/* Function : romInit( int startType ) */
/* */
/* Purpose. : Performs hardware initialization for SBC8xx boards. Is the */
/* entry point for VxWorks in ROM. */
/* */
/* Returns. : None */
/* Notes... : None */
/****************************************************************************/
.text
.align 2
_romInit:
romInit:
bl cold /* jump to the cold boot INIT */
bl start /* jump to the warm boot INIT */
/* copyright notice appears at beginning of ROM (in TEXT segment) */
.ascii "Copyright(c) 2000 HaeDong Information & Communications Co.,Ltd."
.align 2
cold:
xor r0,r0,r0 /* clear R0, default ref register */
mfspr r3,DC_CST /* Insure Data Cache is disabled */
ori r3,r3,0
lis r3,0x0400
mtspr DC_CST,r3
li r3,BOOT_COLD /* set cold boot as start type */
/* r3 should not be altered */
/* */
/* When the PowerPC 860 is powered on, the processor fetches the */
/* instruction located at the address offset IMMR+0x100. */
/* */
lis r4,HIADJ(start) /* load r4 with the address */
addi r4,r4,LO(start) /* of start */
lis r5,HIADJ(romInit) /* load r5 with the address */
addi r5,r5,LO(romInit) /* of romInit() */
lis r6,HIADJ(ROM_TEXT_ADRS) /* load r6 with the address */
addi r6,r6,LO(ROM_TEXT_ADRS) /* of ROM_TEXT_ADRS */
sub r4,r4,r5
add r4,r4,r6
mtspr LR,r4 /* save destination address into */
/* the LR register */
blr /* jump to flash mem address */
start:
/* Set the MSR register to a known state */
xor r4,r4,r4
mtmsr r4
/* DER - clear the Debug Enable Register */
mtspr DER,r4
/* ICR - clear the Interrupt Cause Register */
mtspr ICR, r4
/* ICTRL - initialize the Intstruction Support Control register */
lis r5,HIADJ(0x00000006) /* ICTRL = 6 */
addi r5,r5,LO(0x00000006) /* (background mode operation) */
mtspr ICTRL,r5
/* Disable, unlock, and invalidate the instruction/data cache */
lis r4,HIADJ( CACHE_DISABLE_CMD) /* load disable cmd */
addi r4,r4,LO(CACHE_DISABLE_CMD)
mtspr IC_CST,r4 /* disable the data cache */
mtspr DC_CST,r4 /* disable the instr cache */
lis r4,HIADJ(CACHE_UNLOCK_ALL) /* load unlock cmd */
addi r4,r4,LO(CACHE_UNLOCK_ALL)
mtspr IC_CST,r4 /* unlock all I cache lines */
mtspr DC_CST,r4 /* unlock all D cache lines */
lis r4,HIADJ(CACHE_INVALIDATE_ALL) /* load invalidate cmd */
addi r4,r4,LO(CACHE_INVALIDATE_ALL)
mtspr IC_CST,r4 /* invalidate all I cache lines */
mtspr DC_CST,r4 /* invalidate all D cache lines */
/* Set up MSR for Recoverable Interrupts and Machine Check Enable */
lis r4,HIADJ(0x00001002)
addi r4,r4,LO(0x00001002)
mtmsr r4
/* Set r4 to IMMR contents. SIM accessess will be r4 relative. */
/* */
/* To insure software and silicon are in sync, reload with r4 */
/* with the upper 16 bits of IMMR. */
/* */
/* Note, r4 should not be altered from this point on. */
/* */
lis r4,HIADJ(INTERNAL_MEM_MAP_ADDR)
addi r4,r4,LO(INTERNAL_MEM_MAP_ADDR)
mtspr IMMR,r4
mfspr r4,IMMR
rlwinm r4, r4, 0, 0, 15
/* Setup SYPCR for normal and proper background mode operation */
lis r5,HI(0xffffff03)
addi r5,r5,LO(0xffffff03)
stw r5,SYPCR(0)(r4)
/* Setup TBSCR to hault when freeze is asserted */
lis r5,HIADJ( TBSCR_REFA | TBSCR_REFB | TBSCR_TBF ) /* 0x000000c2 */
addi r5,r5,LO( TBSCR_REFA | TBSCR_REFB | TBSCR_TBF ) /* 0x000000c2 */
stw r5,TBSCR(0)(r4)
/* Setup PISCR to hault when freeze is asserted */
lis r5,HIADJ( PISCR_PS | PISCR_PITF ) /* 0x00000082 */
addi r5,r5,LO( PISCR_PS | PISCR_PITF ) /* 0x00000082 */
stw r5,PISCR(0)(r4)
lis r5,HIADJ(0x01e10940)
addi r5,r5,LO(0x01e10940)
stw r5,SIUMCR(0)(r4)
/* Initialized SIMASK register */
li r5,0x0000
stw r5,SIMASK(0)(r4)
/*----------------------------------*/
/* Memory Controller Initialization */
/*----------------------------------*/
/* Initialize Unused Chip Selects CS1/CS3/CS4/CS5/CS6/CS7 */
lis r5, HIADJ (0x00000000)
addi r5,r5, LO (0x00000000)
stw r5,BR1(0)(r4)
stw r5,OR1(0)(r4)
stw r5,BR3(0)(r4)
stw r5,OR3(0)(r4)
stw r5,BR4(0)(r4)
stw r5,OR4(0)(r4)
stw r5,BR5(0)(r4)
stw r5,OR5(0)(r4)
stw r5,BR6(0)(r4)
stw r5,OR6(0)(r4)
stw r5,BR7(0)(r4)
stw r5,OR7(0)(r4)
/* Initialize Chip Select CS0 */
lis r5,HIADJ(0xffe00901)
addi r5,r5,LO(0xffe00901)
stw r5,BR0(0)(r4)
lis r5,HIADJ(0xffe00160)
addi r5,r5,LO(0xffe00160)
stw r5,OR0(0)(r4)
/*
lis r5,HIADJ(0x10000001)
addi r5,r5,LO(0x10000001)
stw r5,BR1(0)(r4)
lis r5,HIADJ(0xffe00110)
addi r5,r5,LO(0xffe00110)
stw r5,OR1(0)(r4)
*/
/* Initialize Chip Select CS2 */
lis r5,HIADJ(0xFF000A00)
ori r5,r5,LO(0xFF000A00)
stw r5,OR2(0)(r4)
lis r5,HIADJ(0x00000081)
ori r5,r5,LO(0x00000081)
stw r5,BR2(0)(r4)
/*----------------------*/
/* SDRAM Initialization */
/*----------------------*/
/* Load the UPMA DRAM controller CS2 SDRAM */
lis r6, HIADJ(UpmMdrTable) /* point R6 to parameter table */
addi r6,r6, LO(UpmMdrTable) /* point R7 to end parameter table */
lis r7, HIADJ(UpmMdrTableEnd)
addi r7,r7, LO(UpmMdrTableEnd)
lis r11, HIADJ(UpmMcrTable)
addi r11,r11, LO(UpmMcrTable)
contUpmInitA:
sub r5,r7,r6 /* UpmTableEnd - UpmTable */
srawi r5,r5,2 /* divide by 4 */
/* Convert UpmTable to ROM basd addressing */
lis r7, HIADJ(romInit)
addi r7,r7, LO(romInit)
lis r8, HIADJ(ROM_TEXT_ADRS)
addi r8,r8, LO(ROM_TEXT_ADRS)
sub r6,r6,r7 /* subtract romInit base address */
add r6,r6,r8 /* add in ROM_TEXT_ADRS address */
sub r11,r11,r7 /* subtract romInit base address */
add r11,r11,r8 /* add in ROM_TEXT_ADRS address */
lis r9, 0
UpmWriteLoopA:
lwz r10, 0(r6) /* get data from table */
stw r10, MDR(0)(r4) /* store the data to MD register */
lwz r10, 0(r11) /* get data from table */
stw r10, MCR(0)(r4) /* issue command to MCR register */
addi r6,r6,4 /* next entry in the table */
addi r11,r11,4 /* next entry in the table */
addi r9,r9,1 /* next MAD address */
cmpw r9,r5 /* See if we are done yet */
blt UpmWriteLoopA
li r5,0x0400
sth r5,MPTPR(0)(r4)
lis r5,0xD080
ori r5,r5,0x2114
stw r5,MAMR(0)(r4)
lis r5,0x8000
ori r5,r5,0x4105
stw r5,MCR(0)(r4)
lis r5,0x8000
ori r5,r5,0x4830
stw r5,MCR(0)(r4)
lis r5,0x0000
ori r5,r5,0x0088
stw r5,MAR(0)(r4)
lis r5,0x8000
ori r5,r5,0x4106
stw r5,MCR(0)(r4)
/* Delay to let UPMs stablize */
lis r5, HIADJ (0x00000200)
addi r5, r5, LO(0x00000200)
lis r6, 0x0000
UpmDelayloop:
addi r6, r6, 0x01
cmpw cr0, r6, r5
bne UpmDelayloop
/*--------------------------*/
/* SDRAM Initialization End */
/*--------------------------*/
#if CLK50MHZ
lis r6, HIADJ (0x0090c000)
addi r6, r6, LO(0x0090c000)
stw r6, PLPRCR(0)(r4)
#endif
#if CLK65MHZ
lis r6, HIADJ (0x00c0c000)
addi r6, r6, LO(0x00c0c000)
stw r6, PLPRCR(0)(r4)
#endif
#if CLK80MHZ
lis r6, HIADJ (0x00f0c000)
addi r6, r6, LO(0x00f0c000)
stw r6, PLPRCR(0)(r4)
#endif
/* Initialize the stack pointer */
lis sp, HIADJ(STACK_ADRS)
addi sp, sp, LO(STACK_ADRS)
/* Setup a psuedo stack frame for the function call. */
addi sp, sp, -FRAMEBASESZ /* get frame stack */
/* calculate C entry point: routine - entry point + ROM base */
/* routine : romStart */
/* entry point : romInit = R7 */
/* ROM base : ROM_TEXT_ADRS = R8 */
/* C entry point : romStart - R7 + R8 */
/* */
lis r7, HIADJ(romInit)
addi r7,r7, LO(romInit)
lis r8, HIADJ(ROM_TEXT_ADRS)
addi r8,r8, LO(ROM_TEXT_ADRS)
lis r6, HIADJ(romStart) /* load R6 with C entry point */
addi r6,r6, LO(romStart) /* */
sub r6,r6,r7 /* routine - entry point */
add r6,r6,r8 /* + ROM base */
mtlr r6 /* move C entry point to LR */
blr /* jump to the C entry point */
UpmMcrTable:
/* Single Read. (offset 0x0-0x4 in UPM RAM) */
.long 0x00004000
.long 0x00004001
.long 0x00004002
.long 0x00004003
.long 0x00004004
/* Precharge and MRS(offset 0x5-0x7 in UPM RAM) */
.long 0x00004005
.long 0x00004006
.long 0x00004007
/* Burst Read. (offset 0x8-0xf in UPM RAM). */
.long 0x00004008
.long 0x00004009
.long 0x0000400a
.long 0x0000400b
.long 0x0000400c
.long 0x0000400d
.long 0x0000400e
.long 0x0000400f
/* Single Write. (offset 0x18-0x1F in UPM RAM) */
.long 0x00004018
.long 0x00004019
.long 0x0000401a
.long 0x0000401b
/* Burst Write. (offset 20-2F in UPM RAM) */
.long 0x00004020
.long 0x00004021
.long 0x00004022
.long 0x00004023
.long 0x00004024
.long 0x00004025
.long 0x00004026
/* Refresh timer expired (offset 30-3B in UPM RAM) */
.long 0x00004130
.long 0x00004031
.long 0x00004032
.long 0x00004033
.long 0x00004034
.long 0x00004035
/* Exception. (offset 3c-3f in UPM RAM) */
.long 0x0000403c
UpmMcrTableEnd:
UpmMdrTable:
/* Single Read. (offset 0x0-0x4 in UPM RAM) */
.long 0x1F07FC04
.long 0xEEAEFC04
.long 0x11ADFC04
.long 0xEFBBBC00
.long 0x1FF77C47
/* Precharge and MRS(offset 0x5-0x7 in UPM RAM) */
.long 0x1FF77C35
.long 0xEFEABC34
.long 0x1FB57C35
/* Burst Read. (offset 0x8-0xf in UPM RAM). */
.long 0x1F07FC04
.long 0xEEAEFC04
.long 0x10ADFC04
.long 0xF0AFFC00
.long 0xF0AFFC00
.long 0xF1AFFC00
.long 0xEFBBBC00
.long 0x1FF77C47
/* Single Write. (offset 0x18-0x1F in UPM RAM) */
.long 0x1F27FC04
.long 0xEEAEBC00
.long 0x01B93C04
.long 0x1FF77C47
/* Burst Write. (offset 20-2F in UPM RAM) */
.long 0x1F07FC04
.long 0xEEAEBC00
.long 0x10AD7C00
.long 0xF0AFFC00
.long 0xF0AFFC00
.long 0xE1BBBC04
.long 0x1FF77C47
/* Refresh timer expired (offset 30-3B in UPM RAM) */
.long 0x1FF5FC84
.long 0xFFFFFC04
.long 0xFFFFFC04
.long 0xFFFFFC04
.long 0xFFFFFC84
.long 0xFFFFFC07
/* Exception. (offset 3c-3f in UPM RAM) */
.long 0x7FFFFC07
UpmMdrTableEnd:⌨️ 快捷键说明
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