sysalib.s

Tornado 2.0 BSP for HaeDong HD860-R3 韩国HaeDong公司开发的基于Motorola的MPC860处理器的开发板的BSP

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/*                                                                          */
/* Copyright 1988-1996 Emebbed Systems Tools Corporation                    */
/*                                                                          */
/* Filename : sysALib.s                                                     */
/*                                                                          */
/* Purpose. : This module the assembly language based system dependent      */
/*            functions.                                                    */
/*                                                                          */
/****************************************************************************/

/*********************************/
/*                               */
/* Include files                 */
/*                               */
/*********************************/

#define _ASMLANGUAGE                   /* Indicate writing in assembler     */

#include "vxWorks.h"
#include "cacheLib.h"
#include "sysLib.h"
#include "config.h"
#include "regs.h"        
#include "asm.h"
#include "drv/multi/ppc860Siu.h"

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/*                               */
/* Useful defines                */
/*                               */
/*********************************/

#define MSR_IP  25

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/*                               */
/* Global functions defined here */
/*                               */
/*********************************/

        .globl _sysInit                 /* start of system code             */

/*********************************/
/*                               */
/* External functions referenced */
/*                               */
/*********************************/

        .extern usrInit                 /* Only routine called              */
        
/****************************************************************************/
/*                                                                          */
/* Function : sysInit( void )                                               */
/*                                                                          */
/* Purpose. : This is the system start-up entry point for VxWorks in        */
/*            RAM,  the first code executed after booting.  Disables        */
/*            interrupts, sets up the stack,  jumps to the C routine        */
/*            usrInit() in usrConfig.c . The initial stack is set to        */
/*            grow down from the address of sysInit().                      */
/*                                                                          */
/* Returns. : N/A                                                           */
/*                                                                          */
/* Notes... : Should not be called by the user                              */
/*                                                                          */
/****************************************************************************/

        .text
_sysInit:
       /* Disable external interrupts */
       mfmsr   r3                             /* p0 = msr                  */
       INT_MASK(r3, r5)                       /* mask EE bit               */
       rlwinm   r5, r5, 0, _PPC_MSR_BIT_DR + 1, _PPC_MSR_BIT_IR - 1
       rlwinm  r5, r5, 0, _PPC_MSR_BIT_IP + 1, _PPC_MSR_BIT_IP - 1
       mtmsr   r5                              /* msr = p1                 */
       isync                                   /* ISYNC */

        /* Initialize the IMMR register  */
        lis     r4, HIADJ( INTERNAL_MEM_MAP_ADDR)        
        addi    r4, r4, LO(INTERNAL_MEM_MAP_ADDR)
        mtspr   IMMR, r4   

        /* Setup TBSCR to hault when freeze is asserted  */
/*
        lis   r5,HIADJ( TBSCR_TBF )
        addi  r5,r5,LO( TBSCR_TBF ) 
*/
        lis   r5,HIADJ( TBSCR_REFA | TBSCR_REFB | TBSCR_TBF ) /* 0x000000c2 */
        addi  r5,r5,LO( TBSCR_REFA | TBSCR_REFB | TBSCR_TBF ) /* 0x000000c2 */

        stw   r5,TBSCR(0)(r4)

#if FALSE
        Typically the RTF bit should be set to halt the RTC when
  	    an EST Emulator is connected, but due to a silicon mask 
  	    bug, it has been intentionally left out.
  
        /* Setup RTCSC to hault when freeze is asserted  */
        lis   r5,HIADJ( RTCSC_RTF )
        addi  r5,r5,LO( RTCSC_RTF ) 
        stw   r5,RTCSC(0)(r4)
#endif

        /* Setup PISCR to hault when freeze is asserted  */
/*
        lis   r5,HIADJ( PISCR_PITF )
        addi  r5,r5,LO( PISCR_PITF ) 
*/
        lis   r5,HIADJ( PISCR_PS | PISCR_PITF ) /* 0x00000082 */
        addi  r5,r5,LO( PISCR_PS | PISCR_PITF ) /* 0x00000082 */

        stw   r5,PISCR(0)(r4)

        /* Decrementer Exception  */
        lis     r5, HIADJ (0x4C000064)
        addi    r5, r5, LO(0x4C000064)  /* load rfi (0x4c000064) to      */
        stw     r5, 0x900(r0)           /* store rfi at 0x00000900       */

        /*                                                                  */
        /* disable instruction and data caches                              */
        /*                                                                  */
        lis     r5, HIADJ (CACHE_CMD_DISABLE)   /* Disable setting          */
        addi    r5,r5, LO (CACHE_CMD_DISABLE)
        mtspr   IC_CST, r5              /* Disable the Instruction cache    */
        mtspr   DC_CST, r5              /* Disable the Data        cache    */

        lis     r5, HIADJ ( CACHE_CMD_UNLOCK_ALL )   /* Unlock setting          */
        addi    r5, r5, LO (CACHE_CMD_UNLOCK_ALL )
        mtspr   IC_CST, r5              /* Unlock the Instruction cache     */
        mtspr   DC_CST, r5              /* Unlock the Data        cache     */

        lis     r5, HIADJ (CACHE_CMD_INVALIDATE) /* Invalidate setting               */
        addi    r5, r5, LO (CACHE_CMD_INVALIDATE )
        mtspr   IC_CST, r5               /* Invalidate the Instruction cache */
        mtspr   DC_CST, r5               /* Invalidate the Data        cache */

        /* invalidate entries within both TLBs */
        tlbia
     
        /*                                                                  */
        /* initialize the stack pointer                                     */
        /*                                                                  */
        lis     sp, HIADJ (RAM_LOW_ADRS)         /* sysInit() high portion   */
        addi    sp, sp, LO(RAM_LOW_ADRS)        /* sysInit() low  portion   */

        /*                                                                  */
        /* set the default boot code                                        */
        /*                                                                  */
        lis     r3, HIADJ (BOOT_WARM_AUTOBOOT)  /* NORMAL high portion      */
        addi    r3, r3, LO(BOOT_WARM_AUTOBOOT)  /* NORMAL low  portion      */
        
        /*  jump to usrInit */
        addi    sp, sp, -FRAMEBASESZ    /* carve out a starting stack frame */
        b       usrInit                 /* never returns - starts up kernel */