led.v

来自「利用FPGA来实现一个简单的医疗呼叫系统」· Verilog 代码 · 共 80 行

module led(
          clk,      //the clk
          rst,      //the reset
          en,
          end_check,//检测信号是否检测完毕的信号
          require,  //用户请求信号
          led_flag, //是否有错误信号，0没错误，1有错误
          led_red,  //the red light 
          led_green //the green light
          );
input clk;
input rst;
input en;
input end_check;
input require;
input led_flag;
output led_red;
output led_green;

reg led_red;
reg led_green;

always @(posedge clk or negedge rst)
begin
     if(!rst)
     begin
     led_red<=1'b0;
     end
else begin
     if(require==1'b1)//接收到一个请求信号
     led_red<=1'b0;   //红灯亮，说明有请求信号
     else
     led_red<=1'b1;   //红灯不亮，说明没有请求信号
     end
end


reg[5:0]cnt;
reg[15:0]cnt2;

always @(posedge clk or negedge rst)
begin
     if(!rst)
     begin
     led_green<=1'b0;
     cnt<=6'b000000;
     end

else if(en==1'b1)
     begin
          if(end_check==1'b0)
          begin   
               if(led_flag==1'b0)led_green<=1'b0;
          else 
               led_green<=1'b0;
          end
     else begin
               if(led_flag==1'b0)led_green<=1'b1;
          else 
               led_green<=1'b0;
          end
     end
else if(en==1'b0)
     begin
               if(end_check==1'b0)
          begin   
               if(led_flag==1'b0)led_green<=1'b1;
          else 
               led_green<=1'b0;
          end
     else begin
               if(led_flag==1'b0)led_green<=1'b1;
          else 
               led_green<=1'b0;
          end
     end
end

endmodule