counter60.tan.qmsg

这是我们做的一个作业 摸60计数器

{ "Info" "ITDB_FULL_TCO_RESULT" "clk cout 74390:inst\|32 25.110 ns register " "Info: tco from clock \"clk\" to destination pin \"cout\" through register \"74390:inst\|32\" is 25.110 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 19.464 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 19.464 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_27 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_27; Fanout = 1; CLK Node = 'clk'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "" { clk } "NODE_NAME" } "" } } { "counter60.bdf" "" { Schematic "D:/My Documents/My Designs/eda/counter60/counter60.bdf" { { 88 -32 136 104 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.816 ns) + CELL(0.935 ns) 3.220 ns 74390:inst\|7 2 REG LC_X1_Y4_N2 6 " "Info: 2: + IC(0.816 ns) + CELL(0.935 ns) = 3.220 ns; Loc. = LC_X1_Y4_N2; Fanout = 6; REG Node = '74390:inst\|7'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "1.751 ns" { clk 74390:inst|7 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 456 520 584 536 "7" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.226 ns) + CELL(0.935 ns) 5.381 ns 74390:inst\|3 3 REG LC_X3_Y4_N5 5 " "Info: 3: + IC(1.226 ns) + CELL(0.935 ns) = 5.381 ns; Loc. = LC_X3_Y4_N5; Fanout = 5; REG Node = '74390:inst\|3'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "2.161 ns" { 74390:inst|7 74390:inst|3 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 72 520 584 152 "3" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.820 ns) + CELL(0.292 ns) 6.493 ns 74390:inst\|20 4 COMB LC_X4_Y4_N8 1 " "Info: 4: + IC(0.820 ns) + CELL(0.292 ns) = 6.493 ns; Loc. = LC_X4_Y4_N8; Fanout = 1; COMB Node = '74390:inst\|20'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "1.112 ns" { 74390:inst|3 74390:inst|20 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 344 408 472 384 "20" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.724 ns) + CELL(0.935 ns) 8.152 ns 74390:inst\|6 5 REG LC_X3_Y4_N9 6 " "Info: 5: + IC(0.724 ns) + CELL(0.935 ns) = 8.152 ns; Loc. = LC_X3_Y4_N9; Fanout = 6; REG Node = '74390:inst\|6'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "1.659 ns" { 74390:inst|20 74390:inst|6 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 328 520 584 408 "6" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.786 ns) + CELL(0.935 ns) 9.873 ns 74390:inst\|5 6 REG LC_X2_Y4_N2 5 " "Info: 6: + IC(0.786 ns) + CELL(0.935 ns) = 9.873 ns; Loc. = LC_X2_Y4_N2; Fanout = 5; REG Node = '74390:inst\|5'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "1.721 ns" { 74390:inst|6 74390:inst|5 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 200 520 584 280 "5" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.204 ns) + CELL(0.590 ns) 11.667 ns inst2~19 7 COMB LC_X4_Y4_N4 1 " "Info: 7: + IC(1.204 ns) + CELL(0.590 ns) = 11.667 ns; Loc. = LC_X4_Y4_N4; Fanout = 1; COMB Node = 'inst2~19'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "1.794 ns" { 74390:inst|5 inst2~19 } "NODE_NAME" } "" } } { "counter60.bdf" "" { Schematic "D:/My Documents/My Designs/eda/counter60/counter60.bdf" { { 40 576 640 120 "inst2" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.129 ns) + CELL(0.935 ns) 13.731 ns 74390:inst\|34 8 REG LC_X6_Y4_N2 5 " "Info: 8: + IC(1.129 ns) + CELL(0.935 ns) = 13.731 ns; Loc. = LC_X6_Y4_N2; Fanout = 5; REG Node = '74390:inst\|34'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "2.064 ns" { inst2~19 74390:inst|34 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 1016 520 584 1096 "34" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.265 ns) + CELL(0.935 ns) 15.931 ns 74390:inst\|31 9 REG LC_X4_Y4_N5 4 " "Info: 9: + IC(1.265 ns) + CELL(0.935 ns) = 15.931 ns; Loc. = LC_X4_Y4_N5; Fanout = 4; REG Node = '74390:inst\|31'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "2.200 ns" { 74390:inst|34 74390:inst|31 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 632 520 584 712 "31" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.515 ns) + CELL(0.114 ns) 16.560 ns 74390:inst\|29 10 COMB LC_X4_Y4_N9 1 " "Info: 10: + IC(0.515 ns) + CELL(0.114 ns) = 16.560 ns; Loc. = LC_X4_Y4_N9; Fanout = 1; COMB Node = '74390:inst\|29'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "0.629 ns" { 74390:inst|31 74390:inst|29 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 904 408 472 944 "29" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.472 ns) + CELL(0.935 ns) 17.967 ns 74390:inst\|33 11 REG LC_X4_Y4_N7 5 " "Info: 11: + IC(0.472 ns) + CELL(0.935 ns) = 17.967 ns; Loc. = LC_X4_Y4_N7; Fanout = 5; REG Node = '74390:inst\|33'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "1.407 ns" { 74390:inst|29 74390:inst|33 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 888 520 584 968 "33" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.786 ns) + CELL(0.711 ns) 19.464 ns 74390:inst\|32 12 REG LC_X5_Y4_N2 4 " "Info: 12: + IC(0.786 ns) + CELL(0.711 ns) = 19.464 ns; Loc. = LC_X5_Y4_N2; Fanout = 4; REG Node = '74390:inst\|32'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "1.497 ns" { 74390:inst|33 74390:inst|32 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 760 520 584 840 "32" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.721 ns 49.94 % " "Info: Total cell delay = 9.721 ns ( 49.94 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.743 ns 50.06 % " "Info: Total interconnect delay = 9.743 ns ( 50.06 % )" {  } {  } 0}  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "19.464 ns" { clk 74390:inst|7 74390:inst|3 74390:inst|20 74390:inst|6 74390:inst|5 inst2~19 74390:inst|34 74390:inst|31 74390:inst|29 74390:inst|33 74390:inst|32 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "19.464 ns" { clk clk~out0 74390:inst|7 74390:inst|3 74390:inst|20 74390:inst|6 74390:inst|5 inst2~19 74390:inst|34 74390:inst|31 74390:inst|29 74390:inst|33 74390:inst|32 } { 0.000ns 0.000ns 0.816ns 1.226ns 0.820ns 0.724ns 0.786ns 1.204ns 1.129ns 1.265ns 0.515ns 0.472ns 0.786ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.292ns 0.935ns 0.935ns 0.590ns 0.935ns 0.935ns 0.114ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 760 520 584 840 "32" "" } } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.422 ns + Longest register pin " "Info: + Longest register to pin delay is 5.422 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 74390:inst\|32 1 REG LC_X5_Y4_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y4_N2; Fanout = 4; REG Node = '74390:inst\|32'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "" { 74390:inst|32 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 760 520 584 840 "32" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.134 ns) + CELL(0.442 ns) 1.576 ns inst7~42 2 COMB LC_X4_Y4_N5 1 " "Info: 2: + IC(1.134 ns) + CELL(0.442 ns) = 1.576 ns; Loc. = LC_X4_Y4_N5; Fanout = 1; COMB Node = 'inst7~42'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "1.576 ns" { 74390:inst|32 inst7~42 } "NODE_NAME" } "" } } { "counter60.bdf" "" { Schematic "D:/My Documents/My Designs/eda/counter60/counter60.bdf" { { 152 512 576 264 "inst7" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 1.872 ns inst7 3 COMB LC_X4_Y4_N6 9 " "Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 1.872 ns; Loc. = LC_X4_Y4_N6; Fanout = 9; COMB Node = 'inst7'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "0.296 ns" { inst7~42 inst7 } "NODE_NAME" } "" } } { "counter60.bdf" "" { Schematic "D:/My Documents/My Designs/eda/counter60/counter60.bdf" { { 152 512 576 264 "inst7" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.442 ns) + CELL(2.108 ns) 5.422 ns cout 4 PIN PIN_40 0 " "Info: 4: + IC(1.442 ns) + CELL(2.108 ns) = 5.422 ns; Loc. = PIN_40; Fanout = 0; PIN Node = 'cout'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "3.550 ns" { inst7 cout } "NODE_NAME" } "" } } { "counter60.bdf" "" { Schematic "D:/My Documents/My Designs/eda/counter60/counter60.bdf" { { 200 760 936 216 "cout" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.664 ns 49.13 % " "Info: Total cell delay = 2.664 ns ( 49.13 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.758 ns 50.87 % " "Info: Total interconnect delay = 2.758 ns ( 50.87 % )" {  } {  } 0}  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "5.422 ns" { 74390:inst|32 inst7~42 inst7 cout } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.422 ns" { 74390:inst|32 inst7~42 inst7 cout } { 0.000ns 1.134ns 0.182ns 1.442ns } { 0.000ns 0.442ns 0.114ns 2.108ns } } }  } 0}  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "19.464 ns" { clk 74390:inst|7 74390:inst|3 74390:ins