counter60.tan.qmsg

来自「这是我们做的一个作业 摸60计数器」· QMSG 代码 · 共 9 行 · 第 1/5 页

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "10 " "Warning: Found 10 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "74390:inst\|7 " "Info: Detected ripple clock \"74390:inst\|7\" as buffer" {  } { { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 456 520 584 536 "7" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "74390:inst\|7" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "74390:inst\|3 " "Info: Detected ripple clock \"74390:inst\|3\" as buffer" {  } { { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 72 520 584 152 "3" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "74390:inst\|3" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "74390:inst\|20 " "Info: Detected gated clock \"74390:inst\|20\" as buffer" {  } { { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 344 408 472 384 "20" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "74390:inst\|20" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "74390:inst\|6 " "Info: Detected ripple clock \"74390:inst\|6\" as buffer" {  } { { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 328 520 584 408 "6" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "74390:inst\|6" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "74390:inst\|5 " "Info: Detected ripple clock \"74390:inst\|5\" as buffer" {  } { { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 200 520 584 280 "5" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "74390:inst\|5" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "inst2~19 " "Info: Detected gated clock \"inst2~19\" as buffer" {  } { { "counter60.bdf" "" { Schematic "D:/My Documents/My Designs/eda/counter60/counter60.bdf" { { 40 576 640 120 "inst2" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "inst2~19" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "74390:inst\|31 " "Info: Detected ripple clock \"74390:inst\|31\" as buffer" {  } { { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 632 520 584 712 "31" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "74390:inst\|31" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "74390:inst\|34 " "Info: Detected ripple clock \"74390:inst\|34\" as buffer" {  } { { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 1016 520 584 1096 "34" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "74390:inst\|34" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "74390:inst\|29 " "Info: Detected gated clock \"74390:inst\|29\" as buffer" {  } { { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 904 408 472 944 "29" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "74390:inst\|29" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "74390:inst\|33 " "Info: Detected ripple clock \"74390:inst\|33\" as buffer" {  } { { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 888 520 584 968 "33" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "74390:inst\|33" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register 74390:inst\|33 register 74390:inst\|31 47.55 MHz 21.032 ns Internal " "Info: Clock \"clk\" has Internal fmax of 47.55 MHz between source register \"74390:inst\|33\" and destination register \"74390:inst\|31\" (period= 21.032 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.284 ns + Longest register register " "Info: + Longest register to register delay is 1.284 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 74390:inst\|33 1 REG LC_X4_Y4_N7 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y4_N7; Fanout = 5; REG Node = '74390:inst\|33'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "" { 74390:inst|33 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 888 520 584 968 "33" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.546 ns) + CELL(0.738 ns) 1.284 ns 74390:inst\|31 2 REG LC_X4_Y4_N5 4 " "Info: 2: + IC(0.546 ns) + CELL(0.738 ns) = 1.284 ns; Loc. = LC_X4_Y4_N5; Fanout = 4; REG Node = '74390:inst\|31'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "1.284 ns" { 74390:inst|33 74390:inst|31 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 632 520 584 712 "31" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.738 ns 57.48 % " "Info: Total cell delay = 0.738 ns ( 57.48 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.546 ns 42.52 % " "Info: Total interconnect delay = 0.546 ns ( 42.52 % )" {  } {  } 0}  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "1.284 ns" { 74390:inst|33 74390:inst|31 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.284 ns" { 74390:inst|33 74390:inst|31 } { 0.000ns 0.546ns } { 0.000ns 0.738ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-8.971 ns - Smallest " "Info: - Smallest clock skew is -8.971 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.772 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 8.772 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_27 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_27; Fanout = 1; CLK Node = 'clk'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "" { clk } "NODE_NAME" } "" } } { "counter60.bdf" "" { Schematic "D:/My Documents/My Designs/eda/counter60/counter60.bdf" { { 88 -32 136 104 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.816 ns) + CELL(0.935 ns) 3.220 ns 74390:inst\|7 2 REG LC_X1_Y4_N2 6 " "Info: 2: + IC(0.816 ns) + CELL(0.935 ns) = 3.220 ns; Loc. = LC_X1_Y4_N2; Fanout = 6; REG Node = '74390:inst\|7'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "1.751 ns" { clk 74390:inst|7 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 456 520 584 536 "7" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.220 ns) + CELL(0.292 ns) 4.732 ns inst2~19 3 COMB LC_X4_Y4_N4 1 " "Info: 3: + IC(1.220 ns) + CELL(0.292 ns) = 4.732 ns; Loc. = LC_X4_Y4_N4; Fanout = 1; COMB Node = 'inst2~19'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "1.512 ns" { 74390:inst|7 inst2~19 } "NODE_NAME" } "" } } { "counter60.bdf" "" { Schematic "D:/My Documents/My Designs/eda/counter60/counter60.bdf" { { 40 576 640 120 "inst2" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.129 ns) + CELL(0.935 ns) 6.796 ns 74390:inst\|34 4 REG LC_X6_Y4_N2 5 " "Info: 4: + IC(1.129 ns) + CELL(0.935 ns) = 6.796 ns; Loc. = LC_X6_Y4_N2; Fanout = 5; REG Node = '74390:inst\|34'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "2.064 ns" { inst2~19 74390:inst|34 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 1016 520 584 1096 "34" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.265 ns) + CELL(0.711 ns) 8.772 ns 74390:inst\|31 5 REG LC_X4_Y4_N5 4 " "Info: 5: + IC(1.265 ns) + CELL(0.711 ns) = 8.772 ns; Loc. = LC_X4_Y4_N5; Fanout = 4; REG Node = '74390:inst\|31'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "1.976 ns" { 74390:inst|34 74390:inst|31 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 632 520 584 712 "31" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.342 ns 49.50 % " "Info: Total cell delay = 4.342 ns ( 49.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.430 ns 50.50 % " "Info: Total interconnect delay = 4.430 ns ( 50.50 % )" {  } {  } 0}  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "8.772 ns" { clk 74390:inst|7 inst2~19 74390:inst|34 74390:inst|31 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.772 ns" { clk clk~out0 74390:inst|7 inst2~19 74390:inst|34 74390:inst|31 } { 0.000ns 0.000ns 0.816ns 1.220ns 1.129ns 1.265ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 17.743 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 17.743 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_27 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_27; Fanout = 1; CLK Node = 'clk'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "" { clk } "NODE_NAME" } "" } } { "counter60.bdf" "" { Schematic "D:/My Documents/My Designs/eda/counter60/counter60.bdf" { { 88 -32 136 104 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.816 ns) + CELL(0.935 ns) 3.220 ns 74390:inst\|7 2 REG LC_X1_Y4_N2 6 " "Info: 2: + IC(0.816 ns) + CELL(0.935 ns) = 3.220 ns; Loc. = LC_X1_Y4_N2; Fanout = 6; REG Node = '74390:inst\|7'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "1.751 ns" { clk 74390:inst|7 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 456 520 584 536 "7" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.226 ns) + CELL(0.935 ns) 5.381 ns 74390:inst\|3 3 REG LC_X3_Y4_N5 5 " "Info: 3: + IC(1.226 ns) + CELL(0.935 ns) = 5.381 ns; Loc. = LC_X3_Y4_N5; Fanout = 5; REG Node = '74390:inst\|3'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "2.161 ns" { 74390:inst|7 74390:inst|3 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 72 520 584 152 "3" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.820 ns) + CELL(0.292 ns) 6.493 ns 74390:inst\|20 4 COMB LC_X4_Y4_N8 1 " "Info: 4: + IC(0.820 ns) + CELL(0.292 ns) = 6.493 ns; Loc. = LC_X4_Y4_N8; Fanout = 1; COMB Node = '74390:inst\|20'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "1.112 ns" { 74390:inst|3 74390:inst|20 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 344 408 472 384 "20" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.724 ns) + CELL(0.935 ns) 8.152 ns 74390:inst\|6 5 REG LC_X3_Y4_N9 6 " "Info: 5: + IC(0.724 ns) + CELL(0.935 ns) = 8.152 ns; Loc. = LC_X3_Y4_N9; Fanout = 6; REG Node = '74390:inst\|6'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "1.659 ns" { 74390:inst|20 74390:inst|6 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 328 520 584 408 "6" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.786 ns) + CELL(0.935 ns) 9.873 ns 74390:inst\|5 6 REG LC_X2_Y4_N2 5 " "Info: 6: + IC(0.786 ns) + CELL(0.935 ns) = 9.873 ns; Loc. = LC_X2_Y4_N2; Fanout = 5; REG Node = '74390:inst\|5'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "1.721 ns" { 74390:inst|6 74390:inst|5 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 200 520 584 280 "5" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.204 ns) + CELL(0.590 ns) 11.667 ns inst2~19 7 COMB LC_X4_Y4_N4 1 " "Info: 7: + IC(1.204 ns) + CELL(0.590 ns) = 11.667 ns; Loc. = LC_X4_Y4_N4; Fanout = 1; COMB Node = 'inst2~19'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "1.794 ns" { 74390:inst|5 inst2~19 } "NODE_NAME" } "" } } { "counter60.bdf" "" { Schematic "D:/My Documents/My Designs/eda/counter60/counter60.bdf" { { 40 576 640 120 "inst2" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.129 ns) + CELL(0.935 ns) 13.731 ns 74390:inst\|34 8 REG LC_X6_Y4_N2 5 " "Info: 8: + IC(1.129 ns) + CELL(0.935 ns) = 13.731 ns; Loc. = LC_X6_Y4_N2; Fanout = 5; REG Node = '74390:inst\|34'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "2.064 ns" { inst2~19 74390:inst|34 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 1016 520 584 1096 "34" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.265 ns) + CELL(0.935 ns) 15.931 ns 74390:inst\|31 9 REG LC_X4_Y4_N5 4 " "Info: 9: + IC(1.265 ns) + CELL(0.935 ns) = 15.931 ns; Loc. = LC_X4_Y4_N5; Fanout = 4; REG Node = '74390:inst\|31'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "2.200 ns" { 74390:inst|34 74390:inst|31 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 632 520 584 712 "31" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.515 ns) + CELL(0.114 ns) 16.560 ns 74390:inst\|29 10 COMB LC_X4_Y4_N9 1 " "Info: 10: + IC(0.515 ns) + CELL(0.114 ns) = 16.560 ns; Loc. = LC_X4_Y4_N9; Fanout = 1; COMB Node = '74390:inst\|29'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "0.629 ns" { 74390:inst|31 74390:inst|29 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 904 408 472 944 "29" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.472 ns) + CELL(0.711 ns) 17.743 ns 74390:inst\|33 11 REG LC_X4_Y4_N7 5 " "Info: 11: + IC(0.472 ns) + CELL(0.711 ns) = 17.743 ns; Loc. = LC_X4_Y4_N7; Fanout = 5; REG Node = '74390:inst\|33'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "1.183 ns" { 74390:inst|29 74390:inst|33 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 888 520 584 968 "33" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.786 ns 49.52 % " "Info: Total cell delay = 8.786 ns ( 49.52 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.957 ns 50.48 % " "Info: Total interconnect delay = 8.957 ns ( 50.48 % )" {  } {  } 0}  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "17.743 ns" { clk 74390:inst|7 74390:inst|3 74390:inst|20 74390:inst|6 74390:inst|5 inst2~19 74390:inst|34 74390:inst|31 74390:inst|29 74390:inst|33 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "17.743 ns" { clk clk~out0 74390:inst|7 74390:inst|3 74390:inst|20 74390:inst|6 74390:inst|5 inst2~19 74390:inst|34 74390:inst|31 74390:inst|29 74390:inst|33 } { 0.000ns 0.000ns 0.816ns 1.226ns 0.820ns 0.724ns 0.786ns 1.204ns 1.129ns 1.265ns 0.515ns 0.472ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.292ns 0.935ns 0.935ns 0.590ns 0.935ns 0.935ns 0.114ns 0.711ns } } }  } 0}  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "8.772 ns" { clk 74390:inst|7 inst2~19 74390:inst|34 74390:inst|31 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.772 ns" { clk clk~out0 74390:inst|7 inst2~19 74390:inst|34 74390:inst|31 } { 0.000ns 0.000ns 0.816ns 1.220ns 1.129ns 1.265ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.935ns 0.711ns } } } { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "17.743 ns" { clk 74390:inst|7 74390:inst|3 74390:inst|20 74390:inst|6 74390:inst|5 inst2~19 74390:inst|34 74390:inst|31 74390:inst|29 74390:inst|33 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "17.743 ns" { clk clk~out0 74390:inst|7 74390:inst|3 74390:inst|20 74390:inst|6 74390:inst|5 inst2~19 74390:inst|34 74390:inst|31 74390:inst|29 74390:inst|33 } { 0.000ns 0.000ns 0.816ns 1.226ns 0.820ns 0.724ns 0.786ns 1.204ns 1.129ns 1.265ns 0.515ns 0.472ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.292ns 0.935ns 0.935ns 0.590ns 0.935ns 0.935ns 0.114ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 888 520 584 968 "33" "" } } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 632 520 584 712 "31" "" } } } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 888 520 584 968 "33" "" } } } } { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 632 520 584 712 "31" "" } } } }  } 0}  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "1.284 ns" { 74390:inst|33 74390:inst|31 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.284 ns" { 74390:inst|33 74390:inst|31 } { 0.000ns 0.546ns } { 0.000ns 0.738ns } } } { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "8.772 ns" { clk 74390:inst|7 inst2~19 74390:inst|34 74390:inst|31 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.772 ns" { clk clk~out0 74390:inst|7 inst2~19 74390:inst|34 74390:inst|31 } { 0.000ns 0.000ns 0.816ns 1.220ns 1.129ns 1.265ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.935ns 0.711ns } } } { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "17.743 ns" { clk 74390:inst|7 74390:inst|3 74390:inst|20 74390:inst|6 74390:inst|5 inst2~19 74390:inst|34 74390:inst|31 74390:inst|29 74390:inst|33 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "17.743 ns" { clk clk~out0 74390:inst|7 74390:inst|3 74390:inst|20 74390:inst|6 74390:inst|5 inst2~19 74390:inst|34 74390:inst|31 74390:inst|29 74390:inst|33 } { 0.000ns 0.000ns 0.816ns 1.226ns 0.820ns 0.724ns 0.786ns 1.204ns 1.129ns 1.265ns 0.515ns 0.472ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.292ns 0.935ns 0.935ns 0.590ns 0.935ns 0.935ns 0.114ns 0.711ns } } }  } 0}