counter60.fit.qmsg

这是我们做的一个作业 摸60计数器

{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "10 unused 3.30 1 9 0 " "Info: Number of I/O pins in group: 10 (unused VREF, 3.30 VCCIO, 1 input, 9 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 2 20 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  20 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 28 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use unused 0 26 " "Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  26 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 28 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "0.942 ns register register " "Info: Estimated most critical path is register to register delay of 0.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 74390:inst\|33 1 REG LAB_X4_Y4 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X4_Y4; Fanout = 5; REG Node = '74390:inst\|33'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "" { 74390:inst|33 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 888 520 584 968 "33" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.204 ns) + CELL(0.738 ns) 0.942 ns 74390:inst\|31 2 REG LAB_X4_Y4 4 " "Info: 2: + IC(0.204 ns) + CELL(0.738 ns) = 0.942 ns; Loc. = LAB_X4_Y4; Fanout = 4; REG Node = '74390:inst\|31'" {  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "0.942 ns" { 74390:inst|33 74390:inst|31 } "NODE_NAME" } "" } } { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { { 632 520 584 712 "31" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.738 ns 78.34 % " "Info: Total cell delay = 0.738 ns ( 78.34 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.204 ns 21.66 % " "Info: Total interconnect delay = 0.204 ns ( 21.66 % )" {  } {  } 0}  } { { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "0.942 ns" { 74390:inst|33 74390:inst|31 } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 14 19:27:21 2006 " "Info: Processing ended: Thu Sep 14 19:27:21 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}