counter60.fit.qmsg

这是我们做的一个作业 摸60计数器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 14 19:27:19 2006 " "Info: Processing started: Thu Sep 14 19:27:19 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off counter60 -c counter60 " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off counter60 -c counter60" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "counter60 EP1C3T144C8 " "Info: Selected device EP1C3T144C8 for design \"counter60\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6T144C8 " "Info: Device EP1C6T144C8 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "10 10 " "Info: No exact pin location assignment(s) for 10 pins of 10 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "cout " "Info: Pin cout not assigned to an exact location on the device" {  } { { "counter60.bdf" "" { Schematic "D:/My Documents/My Designs/eda/counter60/counter60.bdf" { { 200 760 936 216 "cout" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "cout" } } } } { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "" { cout } "NODE_NAME" } "" } } { "D:/My Documents/My Designs/eda/counter60/counter60.fld" "" { Floorplan "D:/My Documents/My Designs/eda/counter60/counter60.fld" "" "" { cout } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "q2\[3\] " "Info: Pin q2\[3\] not assigned to an exact location on the device" {  } { { "counter60.bdf" "" { Schematic "D:/My Documents/My Designs/eda/counter60/counter60.bdf" { { 336 264 440 352 "q2\[3..0\]" "" } { 160 320 376 176 "q2\[2\]" "" } { 176 320 376 192 "q2\[3\]" "" } { 328 168 264 344 "q2\[3..0\]" "" } { 128 320 368 144 "q2\[0\]" "" } { 144 320 480 160 "q2\[1\]" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "q2\[3\]" } } } } { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "" { q2[3] } "NODE_NAME" } "" } } { "D:/My Documents/My Designs/eda/counter60/counter60.fld" "" { Floorplan "D:/My Documents/My Designs/eda/counter60/counter60.fld" "" "" { q2[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "q2\[2\] " "Info: Pin q2\[2\] not assigned to an exact location on the device" {  } { { "counter60.bdf" "" { Schematic "D:/My Documents/My Designs/eda/counter60/counter60.bdf" { { 336 264 440 352 "q2\[3..0\]" "" } { 160 320 376 176 "q2\[2\]" "" } { 176 320 376 192 "q2\[3\]" "" } { 328 168 264 344 "q2\[3..0\]" "" } { 128 320 368 144 "q2\[0\]" "" } { 144 320 480 160 "q2\[1\]" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "q2\[2\]" } } } } { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "" { q2[2] } "NODE_NAME" } "" } } { "D:/My Documents/My Designs/eda/counter60/counter60.fld" "" { Floorplan "D:/My Documents/My Designs/eda/counter60/counter60.fld" "" "" { q2[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "q2\[1\] " "Info: Pin q2\[1\] not assigned to an exact location on the device" {  } { { "counter60.bdf" "" { Schematic "D:/My Documents/My Designs/eda/counter60/counter60.bdf" { { 336 264 440 352 "q2\[3..0\]" "" } { 160 320 376 176 "q2\[2\]" "" } { 176 320 376 192 "q2\[3\]" "" } { 328 168 264 344 "q2\[3..0\]" "" } { 128 320 368 144 "q2\[0\]" "" } { 144 320 480 160 "q2\[1\]" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "q2\[1\]" } } } } { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "" { q2[1] } "NODE_NAME" } "" } } { "D:/My Documents/My Designs/eda/counter60/counter60.fld" "" { Floorplan "D:/My Documents/My Designs/eda/counter60/counter60.fld" "" "" { q2[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "q2\[0\] " "Info: Pin q2\[0\] not assigned to an exact location on the device" {  } { { "counter60.bdf" "" { Schematic "D:/My Documents/My Designs/eda/counter60/counter60.bdf" { { 336 264 440 352 "q2\[3..0\]" "" } { 160 320 376 176 "q2\[2\]" "" } { 176 320 376 192 "q2\[3\]" "" } { 328 168 264 344 "q2\[3..0\]" "" } { 128 320 368 144 "q2\[0\]" "" } { 144 320 480 160 "q2\[1\]" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "q2\[0\]" } } } } { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "" { q2[0] } "NODE_NAME" } "" } } { "D:/My Documents/My Designs/eda/counter60/counter60.fld" "" { Floorplan "D:/My Documents/My Designs/eda/counter60/counter60.fld" "" "" { q2[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "q1\[3\] " "Info: Pin q1\[3\] not assigned to an exact location on the device" {  } { { "counter60.bdf" "" { Schematic "D:/My Documents/My Designs/eda/counter60/counter60.bdf" { { 304 264 440 320 "q1\[3..0\]" "" } { 296 168 264 312 "q1\[3..0\]" "" } { 64 320 376 80 "q1\[0\]" "" } { 80 320 424 96 "q1\[1\]" "" } { 88 328 456 104 "q1\[2\]" "" } { 112 320 464 128 "q1\[3\]" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "q1\[3\]" } } } } { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "" { q1[3] } "NODE_NAME" } "" } } { "D:/My Documents/My Designs/eda/counter60/counter60.fld" "" { Floorplan "D:/My Documents/My Designs/eda/counter60/counter60.fld" "" "" { q1[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "q1\[2\] " "Info: Pin q1\[2\] not assigned to an exact location on the device" {  } { { "counter60.bdf" "" { Schematic "D:/My Documents/My Designs/eda/counter60/counter60.bdf" { { 304 264 440 320 "q1\[3..0\]" "" } { 296 168 264 312 "q1\[3..0\]" "" } { 64 320 376 80 "q1\[0\]" "" } { 80 320 424 96 "q1\[1\]" "" } { 88 328 456 104 "q1\[2\]" "" } { 112 320 464 128 "q1\[3\]" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "q1\[2\]" } } } } { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "" { q1[2] } "NODE_NAME" } "" } } { "D:/My Documents/My Designs/eda/counter60/counter60.fld" "" { Floorplan "D:/My Documents/My Designs/eda/counter60/counter60.fld" "" "" { q1[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "q1\[1\] " "Info: Pin q1\[1\] not assigned to an exact location on the device" {  } { { "counter60.bdf" "" { Schematic "D:/My Documents/My Designs/eda/counter60/counter60.bdf" { { 304 264 440 320 "q1\[3..0\]" "" } { 296 168 264 312 "q1\[3..0\]" "" } { 64 320 376 80 "q1\[0\]" "" } { 80 320 424 96 "q1\[1\]" "" } { 88 328 456 104 "q1\[2\]" "" } { 112 320 464 128 "q1\[3\]" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "q1\[1\]" } } } } { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "" { q1[1] } "NODE_NAME" } "" } } { "D:/My Documents/My Designs/eda/counter60/counter60.fld" "" { Floorplan "D:/My Documents/My Designs/eda/counter60/counter60.fld" "" "" { q1[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "q1\[0\] " "Info: Pin q1\[0\] not assigned to an exact location on the device" {  } { { "counter60.bdf" "" { Schematic "D:/My Documents/My Designs/eda/counter60/counter60.bdf" { { 304 264 440 320 "q1\[3..0\]" "" } { 296 168 264 312 "q1\[3..0\]" "" } { 64 320 376 80 "q1\[0\]" "" } { 80 320 424 96 "q1\[1\]" "" } { 88 328 456 104 "q1\[2\]" "" } { 112 320 464 128 "q1\[3\]" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "q1\[0\]" } } } } { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "" { q1[0] } "NODE_NAME" } "" } } { "D:/My Documents/My Designs/eda/counter60/counter60.fld" "" { Floorplan "D:/My Documents/My Designs/eda/counter60/counter60.fld" "" "" { q1[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "clk " "Info: Pin clk not assigned to an exact location on the device" {  } { { "counter60.bdf" "" { Schematic "D:/My Documents/My Designs/eda/counter60/counter60.bdf" { { 88 -32 136 104 "clk" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" "" { Report "D:/My Documents/My Designs/eda/counter60/db/counter60_cmp.qrpt" Compiler "counter60" "UNKNOWN" "V1" "D:/My Documents/My Designs/eda/counter60/db/counter60.quartus_db" { Floorplan "D:/My Documents/My Designs/eda/counter60/" "" "" { clk } "NODE_NAME" } "" } } { "D:/My Documents/My Designs/eda/counter60/counter60.fld" "" { Floorplan "D:/My Documents/My Designs/eda/counter60/counter60.fld" "" "" { clk } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "inst7 Global clock " "Info: Automatically promoted some destinations of signal \"inst7\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "cout " "Info: Destination \"cout\" may be non-global or may not use global clock" {  } { { "counter60.bdf" "" { Schematic "D:/My Documents/My Designs/eda/counter60/counter60.bdf" { { 200 760 936 216 "cout" "" } } } }  } 0}  } { { "counter60.bdf" "" { Schematic "D:/My Documents/My Designs/eda/counter60/counter60.bdf" { { 152 512 576 264 "inst7" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}