counter60.map.qmsg

这是我们做的一个作业 摸60计数器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 14 19:27:17 2006 " "Info: Processing started: Thu Sep 14 19:27:17 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off counter60 -c counter60 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off counter60 -c counter60" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter60.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file counter60.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 counter60 " "Info: Found entity 1: counter60" {  } { { "counter60.bdf" "" { Schematic "D:/My Documents/My Designs/eda/counter60/counter60.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "counter60 " "Info: Elaborating entity \"counter60\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../altera/quartus50/libraries/others/maxplus2/74390.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../altera/quartus50/libraries/others/maxplus2/74390.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74390 " "Info: Found entity 1: 74390" {  } { { "74390.bdf" "" { Schematic "d:/altera/quartus50/libraries/others/maxplus2/74390.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74390 74390:inst " "Info: Elaborating entity \"74390\" for hierarchy \"74390:inst\"" {  } { { "counter60.bdf" "inst" { Schematic "D:/My Documents/My Designs/eda/counter60/counter60.bdf" { { 56 208 320 216 "inst" "" } } } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "24 " "Info: Implemented 24 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "9 " "Info: Implemented 9 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "14 " "Info: Implemented 14 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 14 19:27:17 2006 " "Info: Processing ended: Thu Sep 14 19:27:17 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}