counter60.tan.rpt

这是我们做的一个作业 摸60计数器

; N/A   ; None         ; 18.807 ns  ; 74390:inst|34 ; cout  ; clk        ;
; N/A   ; None         ; 17.331 ns  ; 74390:inst|34 ; q2[0] ; clk        ;
; N/A   ; None         ; 16.037 ns  ; 74390:inst|5  ; cout  ; clk        ;
; N/A   ; None         ; 13.863 ns  ; 74390:inst|5  ; q1[2] ; clk        ;
; N/A   ; None         ; 13.611 ns  ; 74390:inst|6  ; cout  ; clk        ;
; N/A   ; None         ; 11.994 ns  ; 74390:inst|6  ; q1[1] ; clk        ;
; N/A   ; None         ; 11.079 ns  ; 74390:inst|3  ; cout  ; clk        ;
; N/A   ; None         ; 9.613 ns   ; 74390:inst|7  ; cout  ; clk        ;
; N/A   ; None         ; 8.972 ns   ; 74390:inst|3  ; q1[3] ; clk        ;
; N/A   ; None         ; 6.488 ns   ; 74390:inst|7  ; q1[0] ; clk        ;
+-------+--------------+------------+---------------+-------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Thu Sep 14 19:27:25 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off counter60 -c counter60 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 10 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "74390:inst|7" as buffer
    Info: Detected ripple clock "74390:inst|3" as buffer
    Info: Detected gated clock "74390:inst|20" as buffer
    Info: Detected ripple clock "74390:inst|6" as buffer
    Info: Detected ripple clock "74390:inst|5" as buffer
    Info: Detected gated clock "inst2~19" as buffer
    Info: Detected ripple clock "74390:inst|31" as buffer
    Info: Detected ripple clock "74390:inst|34" as buffer
    Info: Detected gated clock "74390:inst|29" as buffer
    Info: Detected ripple clock "74390:inst|33" as buffer
Info: Clock "clk" has Internal fmax of 47.55 MHz between source register "74390:inst|33" and destination register "74390:inst|31" (period= 21.032 ns)
    Info: + Longest register to register delay is 1.284 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y4_N7; Fanout = 5; REG Node = '74390:inst|33'
        Info: 2: + IC(0.546 ns) + CELL(0.738 ns) = 1.284 ns; Loc. = LC_X4_Y4_N5; Fanout = 4; REG Node = '74390:inst|31'
        Info: Total cell delay = 0.738 ns ( 57.48 % )
        Info: Total interconnect delay = 0.546 ns ( 42.52 % )
    Info: - Smallest clock skew is -8.971 ns
        Info: + Shortest clock path from clock "clk" to destination register is 8.772 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_27; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.816 ns) + CELL(0.935 ns) = 3.220 ns; Loc. = LC_X1_Y4_N2; Fanout = 6; REG Node = '74390:inst|7'
            Info: 3: + IC(1.220 ns) + CELL(0.292 ns) = 4.732 ns; Loc. = LC_X4_Y4_N4; Fanout = 1; COMB Node = 'inst2~19'
            Info: 4: + IC(1.129 ns) + CELL(0.935 ns) = 6.796 ns; Loc. = LC_X6_Y4_N2; Fanout = 5; REG Node = '74390:inst|34'
            Info: 5: + IC(1.265 ns) + CELL(0.711 ns) = 8.772 ns; Loc. = LC_X4_Y4_N5; Fanout = 4; REG Node = '74390:inst|31'
            Info: Total cell delay = 4.342 ns ( 49.50 % )
            Info: Total interconnect delay = 4.430 ns ( 50.50 % )
        Info: - Longest clock path from clock "clk" to source register is 17.743 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_27; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.816 ns) + CELL(0.935 ns) = 3.220 ns; Loc. = LC_X1_Y4_N2; Fanout = 6; REG Node = '74390:inst|7'
            Info: 3: + IC(1.226 ns) + CELL(0.935 ns) = 5.381 ns; Loc. = LC_X3_Y4_N5; Fanout = 5; REG Node = '74390:inst|3'
            Info: 4: + IC(0.820 ns) + CELL(0.292 ns) = 6.493 ns; Loc. = LC_X4_Y4_N8; Fanout = 1; COMB Node = '74390:inst|20'
            Info: 5: + IC(0.724 ns) + CELL(0.935 ns) = 8.152 ns; Loc. = LC_X3_Y4_N9; Fanout = 6; REG Node = '74390:inst|6'
            Info: 6: + IC(0.786 ns) + CELL(0.935 ns) = 9.873 ns; Loc. = LC_X2_Y4_N2; Fanout = 5; REG Node = '74390:inst|5'
            Info: 7: + IC(1.204 ns) + CELL(0.590 ns) = 11.667 ns; Loc. = LC_X4_Y4_N4; Fanout = 1; COMB Node = 'inst2~19'
            Info: 8: + IC(1.129 ns) + CELL(0.935 ns) = 13.731 ns; Loc. = LC_X6_Y4_N2; Fanout = 5; REG Node = '74390:inst|34'
            Info: 9: + IC(1.265 ns) + CELL(0.935 ns) = 15.931 ns; Loc. = LC_X4_Y4_N5; Fanout = 4; REG Node = '74390:inst|31'
            Info: 10: + IC(0.515 ns) + CELL(0.114 ns) = 16.560 ns; Loc. = LC_X4_Y4_N9; Fanout = 1; COMB Node = '74390:inst|29'
            Info: 11: + IC(0.472 ns) + CELL(0.711 ns) = 17.743 ns; Loc. = LC_X4_Y4_N7; Fanout = 5; REG Node = '74390:inst|33'
            Info: Total cell delay = 8.786 ns ( 49.52 % )
            Info: Total interconnect delay = 8.957 ns ( 50.48 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Warning: Circuit may not operate. Detected 8 non-operational path(s) clocked by clock "clk" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "74390:inst|32" and destination pin or register "74390:inst|32" for clock "clk" (Hold time is 7.014 ns)
    Info: + Largest clock skew is 8.237 ns
        Info: + Longest clock path from clock "clk" to destination register is 19.464 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_27; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.816 ns) + CELL(0.935 ns) = 3.220 ns; Loc. = LC_X1_Y4_N2; Fanout = 6; REG Node = '74390:inst|7'
            Info: 3: + IC(1.226 ns) + CELL(0.935 ns) = 5.381 ns; Loc. = LC_X3_Y4_N5; Fanout = 5; REG Node = '74390:inst|3'
            Info: 4: + IC(0.820 ns) + CELL(0.292 ns) = 6.493 ns; Loc. = LC_X4_Y4_N8; Fanout = 1; COMB Node = '74390:inst|20'
            Info: 5: + IC(0.724 ns) + CELL(0.935 ns) = 8.152 ns; Loc. = LC_X3_Y4_N9; Fanout = 6; REG Node = '74390:inst|6'
            Info: 6: + IC(0.786 ns) + CELL(0.935 ns) = 9.873 ns; Loc. = LC_X2_Y4_N2; Fanout = 5; REG Node = '74390:inst|5'
            Info: 7: + IC(1.204 ns) + CELL(0.590 ns) = 11.667 ns; Loc. = LC_X4_Y4_N4; Fanout = 1; COMB Node = 'inst2~19'
            Info: 8: + IC(1.129 ns) + CELL(0.935 ns) = 13.731 ns; Loc. = LC_X6_Y4_N2; Fanout = 5; REG Node = '74390:inst|34'
            Info: 9: + IC(1.265 ns) + CELL(0.935 ns) = 15.931 ns; Loc. = LC_X4_Y4_N5; Fanout = 4; REG Node = '74390:inst|31'
            Info: 10: + IC(0.515 ns) + CELL(0.114 ns) = 16.560 ns; Loc. = LC_X4_Y4_N9; Fanout = 1; COMB Node = '74390:inst|29'
            Info: 11: + IC(0.472 ns) + CELL(0.935 ns) = 17.967 ns; Loc. = LC_X4_Y4_N7; Fanout = 5; REG Node = '74390:inst|33'
            Info: 12: + IC(0.786 ns) + CELL(0.711 ns) = 19.464 ns; Loc. = LC_X5_Y4_N2; Fanout = 4; REG Node = '74390:inst|32'
            Info: Total cell delay = 9.721 ns ( 49.94 % )
            Info: Total interconnect delay = 9.743 ns ( 50.06 % )
        Info: - Shortest clock path from clock "clk" to source register is 11.227 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_27; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.816 ns) + CELL(0.935 ns) = 3.220 ns; Loc. = LC_X1_Y4_N2; Fanout = 6; REG Node = '74390:inst|7'
            Info: 3: + IC(1.220 ns) + CELL(0.292 ns) = 4.732 ns; Loc. = LC_X4_Y4_N4; Fanout = 1; COMB Node = 'inst2~19'
            Info: 4: + IC(1.129 ns) + CELL(0.935 ns) = 6.796 ns; Loc. = LC_X6_Y4_N2; Fanout = 5; REG Node = '74390:inst|34'
            Info: 5: + IC(1.235 ns) + CELL(0.292 ns) = 8.323 ns; Loc. = LC_X4_Y4_N9; Fanout = 1; COMB Node = '74390:inst|29'
            Info: 6: + IC(0.472 ns) + CELL(0.935 ns) = 9.730 ns; Loc. = LC_X4_Y4_N7; Fanout = 5; REG Node = '74390:inst|33'
            Info: 7: + IC(0.786 ns) + CELL(0.711 ns) = 11.227 ns; Loc. = LC_X5_Y4_N2; Fanout = 4; REG Node = '74390:inst|32'
            Info: Total cell delay = 5.569 ns ( 49.60 % )
            Info: Total interconnect delay = 5.658 ns ( 50.40 % )
    Info: - Micro clock to output delay of source is 0.224 ns
    Info: - Shortest register to register delay is 1.014 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y4_N2; Fanout = 4; REG Node = '74390:inst|32'
        Info: 2: + IC(0.536 ns) + CELL(0.478 ns) = 1.014 ns; Loc. = LC_X5_Y4_N2; Fanout = 4; REG Node = '74390:inst|32'
        Info: Total cell delay = 0.478 ns ( 47.14 % )
        Info: Total interconnect delay = 0.536 ns ( 52.86 % )
    Info: + Micro hold delay of destination is 0.015 ns
Info: tco from clock "clk" to destination pin "cout" through register "74390:inst|32" is 25.110 ns
    Info: + Longest clock path from clock "clk" to source register is 19.464 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_27; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.816 ns) + CELL(0.935 ns) = 3.220 ns; Loc. = LC_X1_Y4_N2; Fanout = 6; REG Node = '74390:inst|7'
        Info: 3: + IC(1.226 ns) + CELL(0.935 ns) = 5.381 ns; Loc. = LC_X3_Y4_N5; Fanout = 5; REG Node = '74390:inst|3'
        Info: 4: + IC(0.820 ns) + CELL(0.292 ns) = 6.493 ns; Loc. = LC_X4_Y4_N8; Fanout = 1; COMB Node = '74390:inst|20'
        Info: 5: + IC(0.724 ns) + CELL(0.935 ns) = 8.152 ns; Loc. = LC_X3_Y4_N9; Fanout = 6; REG Node = '74390:inst|6'
        Info: 6: + IC(0.786 ns) + CELL(0.935 ns) = 9.873 ns; Loc. = LC_X2_Y4_N2; Fanout = 5; REG Node = '74390:inst|5'
        Info: 7: + IC(1.204 ns) + CELL(0.590 ns) = 11.667 ns; Loc. = LC_X4_Y4_N4; Fanout = 1; COMB Node = 'inst2~19'
        Info: 8: + IC(1.129 ns) + CELL(0.935 ns) = 13.731 ns; Loc. = LC_X6_Y4_N2; Fanout = 5; REG Node = '74390:inst|34'
        Info: 9: + IC(1.265 ns) + CELL(0.935 ns) = 15.931 ns; Loc. = LC_X4_Y4_N5; Fanout = 4; REG Node = '74390:inst|31'
        Info: 10: + IC(0.515 ns) + CELL(0.114 ns) = 16.560 ns; Loc. = LC_X4_Y4_N9; Fanout = 1; COMB Node = '74390:inst|29'
        Info: 11: + IC(0.472 ns) + CELL(0.935 ns) = 17.967 ns; Loc. = LC_X4_Y4_N7; Fanout = 5; REG Node = '74390:inst|33'
        Info: 12: + IC(0.786 ns) + CELL(0.711 ns) = 19.464 ns; Loc. = LC_X5_Y4_N2; Fanout = 4; REG Node = '74390:inst|32'
        Info: Total cell delay = 9.721 ns ( 49.94 % )
        Info: Total interconnect delay = 9.743 ns ( 50.06 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 5.422 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y4_N2; Fanout = 4; REG Node = '74390:inst|32'
        Info: 2: + IC(1.134 ns) + CELL(0.442 ns) = 1.576 ns; Loc. = LC_X4_Y4_N5; Fanout = 1; COMB Node = 'inst7~42'
        Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 1.872 ns; Loc. = LC_X4_Y4_N6; Fanout = 9; COMB Node = 'inst7'
        Info: 4: + IC(1.442 ns) + CELL(2.108 ns) = 5.422 ns; Loc. = PIN_40; Fanout = 0; PIN Node = 'cout'
        Info: Total cell delay = 2.664 ns ( 49.13 % )
        Info: Total interconnect delay = 2.758 ns ( 50.87 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Processing ended: Thu Sep 14 19:27:26 2006
    Info: Elapsed time: 00:00:01