📄 counter60.tan.rpt
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Timing Analyzer report for counter60
Thu Sep 14 19:27:26 2006
Version 5.0 Build 148 04/26/2005 SJ Full Version
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; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. Clock Hold: 'clk'
7. tco
8. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+------------------------------------------+---------------+----------------------------------+---------------+---------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+----------------------------------+---------------+---------------+------------+----------+--------------+
; Worst-case tco ; N/A ; None ; 25.110 ns ; 74390:inst|32 ; cout ; clk ; ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; 47.55 MHz ( period = 21.032 ns ) ; 74390:inst|33 ; 74390:inst|31 ; clk ; clk ; 0 ;
; Clock Hold: 'clk' ; Not operational: Clock Skew > Data Delay ; None ; N/A ; 74390:inst|32 ; 74390:inst|32 ; clk ; clk ; 8 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 8 ;
+------------------------------+------------------------------------------+---------------+----------------------------------+---------------+---------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C3T144C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; NONE ; 0.000 ns ; 0.000 ns ; NONE ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 47.55 MHz ( period = 21.032 ns ) ; 74390:inst|33 ; 74390:inst|31 ; clk ; clk ; None ; None ; 1.284 ns ;
; N/A ; 78.78 MHz ( period = 12.694 ns ) ; 74390:inst|32 ; 74390:inst|31 ; clk ; clk ; None ; None ; 1.741 ns ;
; N/A ; 104.87 MHz ( period = 9.536 ns ) ; 74390:inst|33 ; 74390:inst|33 ; clk ; clk ; None ; None ; 1.038 ns ;
; N/A ; 105.13 MHz ( period = 9.512 ns ) ; 74390:inst|32 ; 74390:inst|32 ; clk ; clk ; None ; None ; 1.014 ns ;
; N/A ; 116.12 MHz ( period = 8.612 ns ) ; 74390:inst|6 ; 74390:inst|3 ; clk ; clk ; None ; None ; 1.274 ns ;
; N/A ; 121.80 MHz ( period = 8.210 ns ) ; 74390:inst|34 ; 74390:inst|34 ; clk ; clk ; None ; None ; 1.014 ns ;
; N/A ; 128.06 MHz ( period = 7.809 ns ) ; 74390:inst|31 ; 74390:inst|31 ; clk ; clk ; None ; None ; 0.613 ns ;
; N/A ; 163.21 MHz ( period = 6.127 ns ) ; 74390:inst|5 ; 74390:inst|3 ; clk ; clk ; None ; None ; 1.374 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74390:inst|6 ; 74390:inst|6 ; clk ; clk ; None ; None ; 1.027 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74390:inst|5 ; 74390:inst|5 ; clk ; clk ; None ; None ; 1.014 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74390:inst|7 ; 74390:inst|7 ; clk ; clk ; None ; None ; 1.014 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; 74390:inst|3 ; 74390:inst|3 ; clk ; clk ; None ; None ; 0.822 ns ;
+-------+------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'clk' ;
+------------------------------------------+---------------+---------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+------------------------------------------+---------------+---------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Not operational: Clock Skew > Data Delay ; 74390:inst|32 ; 74390:inst|32 ; clk ; clk ; None ; None ; 1.014 ns ;
; Not operational: Clock Skew > Data Delay ; 74390:inst|33 ; 74390:inst|33 ; clk ; clk ; None ; None ; 1.038 ns ;
; Not operational: Clock Skew > Data Delay ; 74390:inst|31 ; 74390:inst|31 ; clk ; clk ; None ; None ; 0.613 ns ;
; Not operational: Clock Skew > Data Delay ; 74390:inst|34 ; 74390:inst|34 ; clk ; clk ; None ; None ; 1.014 ns ;
; Not operational: Clock Skew > Data Delay ; 74390:inst|33 ; 74390:inst|31 ; clk ; clk ; None ; None ; 1.284 ns ;
; Not operational: Clock Skew > Data Delay ; 74390:inst|32 ; 74390:inst|31 ; clk ; clk ; None ; None ; 1.741 ns ;
; Not operational: Clock Skew > Data Delay ; 74390:inst|5 ; 74390:inst|5 ; clk ; clk ; None ; None ; 1.014 ns ;
; Not operational: Clock Skew > Data Delay ; 74390:inst|6 ; 74390:inst|6 ; clk ; clk ; None ; None ; 1.027 ns ;
+------------------------------------------+---------------+---------------+------------+----------+----------------------------+----------------------------+--------------------------+
+------------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+---------------+-------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+---------------+-------+------------+
; N/A ; None ; 25.110 ns ; 74390:inst|32 ; cout ; clk ;
; N/A ; None ; 23.727 ns ; 74390:inst|32 ; q2[2] ; clk ;
; N/A ; None ; 22.949 ns ; 74390:inst|33 ; cout ; clk ;
; N/A ; None ; 21.529 ns ; 74390:inst|33 ; q2[1] ; clk ;
; N/A ; None ; 20.155 ns ; 74390:inst|31 ; cout ; clk ;
; N/A ; None ; 19.490 ns ; 74390:inst|31 ; q2[3] ; clk ;
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