second_counter.v

来自「一些很好的FPGA设计实例」· Verilog 代码 · 共 31 行

/* 秒自动计时子模块*/
module second_counter(EN,clk,second_data1,second_data0,EO);
/* 输入输出端口定义*/
output [3:0] second_data1,second_data0;
output EO;
input  clk,EN;
/* 数据类型定义*/
reg [3:0] second_data1,second_data0;
reg EO;
/* 实现60秒钟的计时并且计到60秒钟后自动进位*/
always @(posedge clk)
begin
  if(EN == 1'b1)
    begin
	  if(second_data0 < 4'b1001)
		second_data0 <= second_data0 + 4'b1;
	  else
	  begin
		EO <= 1'b0;
		second_data0 <= 4'b0;
		if(second_data1 < 4'b0101)
		  second_data1 <= second_data1 + 4'b1;
		else
		begin
		  second_data1 <= 4'b0;
		  EO <= 1'b1;
		end
	  end
	end
end
endmodule