fdiv.v

来自「一些很好的FPGA设计实例」· Verilog 代码 · 共 56 行

module fdiv(
			clk,
			f200hz,
			f60hz,
			f1hz
			);
output f200hz,f60hz,f1hz;
input  clk;  //1KHz input

reg f200hz,f60hz,f1hz;
integer CNT1=0,CNT2=0,CNT3=0;
/*将全局时钟48M分频得到200Hz时钟信号*/
always @(posedge clk)
begin
  if(CNT1 < 240000)
  begin
	CNT1 = CNT1 + 1;
	f200hz <= 1'b0;
  end
  else
  begin
    CNT1 = 0;
    f200hz <= 1'b1;
  end  
end
/*将200Hz时钟分频得到60Hz时钟信号*/
always @(posedge f200hz)
begin
  if(CNT2 < 2)
  begin
	CNT2 = CNT2 + 1;
	f60hz <= 1'b0;
  end
  else
  begin
    CNT2 = 0;
    f60hz <= 1'b1;
  end  
end
/*将200Hz时钟分频得到1Hz时钟信号*/
always @(posedge f200hz)
begin
  if(CNT3 < 199)
  begin
	CNT3 = CNT3 + 1;
	f1hz <= 1'b0;
  end
  else
  begin
    CNT3 = 0;
    f1hz <= 1'b1;
  end  
end

endmodule